ice_dpll_sw_...e_adjust_set(9)
πΈ ice_dpll_sw_phase_adjust_set(9) β like, the Kernel API Manual page, bestie π
okay so you're reading the Kernel API Manual entry for ice_dpll_sw_phase_adjust_set(9) and honestly? it's a glow-up moment. buckle up π
β¨ NAME β¨
ice_dpll_sw_phase_adjust_set β the callback that handles setting the SW pin phase adjust value. that's it, that's the whole vibe π¦
β¨ SYNOPSIS β¨
int ice_dpll_sw_phase_adjust_set (const struct dpll_pin *pin , void
*pin_priv , const struct dpll_device *dpll , void *dpll_priv , s32
phase_adjust , struct netlink_ext_ack *extack );
like, yes, that's a lot of parameters. we'll get through it together π«Ά
β¨ ARGUMENTS β¨
pinβ pointer to a pin. the main character of this function ngl πpin_privβ the private data pointer that got passed on pin registration. it's giving "you had to be there" πdpllβ registered dpll pointer. iconic pointer, no notes β¨dpll_privβ private data pointer that was passed on dpll registration. siblings withpin_privfr fr πphase_adjustβ the phase_adjust value that's going to be set. this is the whole point of the function, lowkey πextackβ error reporting. the friend that tells everyone what went wrong π
β¨ DESCRIPTION β¨
it's a Dpll subsystem callback, bestie. what does it do? it wraps a handler for setting phase adjust on an output pin. that's the tea β highkey simple, but it's doing the work behind the scenes like the quiet friend who actually has their life together π
β¨ CONTEXT β¨
okay this is the important one β it calls a function which acquires and releases pf->dplls.lock. so like, lock goes on, lock goes off. don't come for it about the lock, it's handled πβ¨
β¨ RETURN β¨
a return value vibe check:
0β success π slay- negative β error π that's it, that's the whole range
β¨ SEE ALSO β¨
grab a snack bestie, this list is long π but every single one goes here, no skipping β that's the rule:
- Kernel file
./drivers/net/ethernet/intel/ice/ice_dpll.c - enum
ice_dpll_pin_type(9) ice_dpll_is_sw_pin(9)ice_dpll_is_reset(9)ice_dpll_pin_freq_set(9)ice_dpll_frequency_set(9)ice_dpll_input_frequency_set(9)ice_dpll_output_frequency_set(9)ice_dpll_frequency_get(9)ice_dpll_input_frequency_get(9)ice_dpll_output_frequency_get(9)ice_dpll_sw_pin_frequency_set(9)ice_dpll_sw_pin_frequency_get(9)ice_dpll_pin_enable(9)ice_dpll_pin_disable(9)ice_dpll_pin_store_state(9)ice_dpll_rclk_update_e825c(9)ice_dpll_rclk_update(9)ice_dpll_sw_pins_update(9)ice_dpll_pin_state_update(9)ice_dpll_hw_input_prio_set(9)ice_dpll_lock_status_get(9)ice_dpll_mode_get(9)ice_dpll_phase_offset_monitor_set(9)ice_dpll_phase_offset_monitor_get(9)ice_dpll_pin_state_set(9)ice_dpll_output_state_set(9)ice_dpll_input_state_set(9)ice_dpll_pin_state_get(9)ice_dpll_output_state_get(9)ice_dpll_input_state_get(9)ice_dpll_sw_pin_notify_peer(9)ice_dpll_sma_direction_set(9)ice_dpll_ufl_pin_state_set(9)ice_dpll_sw_pin_state_get(9)ice_dpll_sma_pin_state_set(9)ice_dpll_input_prio_get(9)ice_dpll_input_prio_set(9)ice_dpll_input_direction(9)ice_dpll_output_direction(9)ice_dpll_pin_sma_direction_set(9)ice_dpll_pin_sw_direction_get(9)ice_dpll_pin_phase_adjust_get(9)ice_dpll_pin_phase_adjust_set(9)ice_dpll_input_phase_adjust_set(9)ice_dpll_output_phase_adjust_set(9)ice_dpll_sw_phase_adjust_get(9)ice_dpll_phase_offset_get(9)ice_dpll_synce_update_e825c(9)ice_dpll_output_esync_set(9)ice_dpll_output_esync_get(9)ice_dpll_input_esync_set(9)ice_dpll_input_esync_get(9)ice_dpll_sw_esync_set(9)ice_dpll_sw_esync_get(9)ice_dpll_input_ref_sync_get(9)ice_dpll_sw_input_ref_sync_get(9)ice_dpll_rclk_state_on_pin_set(9)ice_dpll_rclk_state_on_pin_get(9)ice_dpll_txclk_work(9)ice_dpll_txclk_state_on_dpll_set(9)ice_dpll_txclk_state_on_dpll_get(9)ice_generate_clock_id(9)ice_dpll_pin_ntf(9)ice_dpll_notify_changes(9)ice_dpll_is_pps_phase_monitor(9)ice_dpll_pins_notify_mask(9)ice_dpll_pps_update_phase_offsets(9)ice_dpll_update_state(9)ice_dpll_periodic_work(9)ice_dpll_init_ref_sync_inputs(9)ice_dpll_release_pins(9)ice_dpll_get_pins(9)ice_dpll_unregister_pins(9)ice_dpll_pin_ref_sync_register(9)ice_dpll_register_pins(9)ice_dpll_deinit_direct_pins(9)ice_dpll_init_direct_pins(9)ice_dpll_deinit_rclk_pin(9)ice_dpll_init_pin_common(9)ice_dpll_init_rclk_pin(9)ice_dpll_deinit_pins(9)ice_dpll_init_fwnode_pins(9)ice_dpll_init_pins_e825(9)ice_dpll_init_pins(9)ice_dpll_deinit_dpll(9)ice_dpll_init_dpll(9)ice_dpll_deinit_worker(9)ice_dpll_init_worker(9)ice_dpll_phase_range_set(9)ice_dpll_init_info_pins_generic(9)ice_dpll_init_info_direct_pins(9)ice_dpll_init_info_pin_on_pin_e825c(9)ice_dpll_init_info_rclk_pin(9)ice_dpll_init_info_sw_pins(9)ice_dpll_init_info_txclk_pins_e825c(9)ice_dpll_init_pins_info(9)ice_dpll_deinit_info(9)ice_dpll_init_info_e825c(9)ice_dpll_init_info(9)ice_dpll_deinit(9)ice_dpll_init_e825(9)ice_dpll_init_e810(9)
ok that's the whole page, you ate that π go forth and adjust phases responsibly, bestie π
and that's a wrap on the Kernel API Manual entry for ice_dpll_sw_phase_adjust_set(9), straight out of ./drivers/net/ethernet/intel/ice, dated October 2026 β¨ mwah, bye π§π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms