ice_dpll_inp...requency_set(9)

💅 ice_dpll_inp...requency_set(9) — from the Kernel API Manual (yes bestie, that truncated title is literally the title, no cap)

okay so picture this: you're deep in the kernel API man pages, the section 9 girlies, and you open this absolute icon of a page. it's ice_dpll_input_frequency_set, and she is the input pin callback for setting frequency. 🎀

---

✨ NAME ✨

ice_dpll_input_frequency_set — input pin callback for set frequency 🌸

---

🦋 SYNOPSIS 🦋

int ice_dpll_input_frequency_set (const struct dpll_pin *pin , void
*pin_priv , const struct dpll_device *dpll , void *dpll_priv , u64
frequency , struct netlink_ext_ack *extack );

like, the whole gang's here, everybody say hi 👑

---

💖 ARGUMENTS 💖

• pin — pointer to a pin. just a lil pointer, she's pointing at a pin 🫶
• pin_priv — private data pointer passed on pin registration. the pin's personal lore, handed over at registration time
• dpll — pointer to dpll
• dpll_priv — private data pointer passed on dpll registration. same vibe, different registration bestie
• frequency — frequency to be set. the actual number, the main character of this whole function honestly
• extack — error reporting. she's the one who tells you when things go sideways 💀

---

🌈 DESCRIPTION 🌈

Wraps internal set frequency command on a pin. that's it, that's the whole description, and honestly? she ate. simple, direct, no notes ✨

---

🔥 CONTEXT 🔥

Calls a function which acquires pf->dplls.lock

bestie read that again — there's a lock in play. this is not a "call me from wherever, whenever, it's fine" situation. it's giving "I'm acquiring pf->dplls.lock" energy, so respect the lock, periodt 🔒

---

👑 RETURN 👑

• 0 — success 🎉
• negative — error pin not found or couldn't set in hw 😭

---

💜 SEE ALSO 💜

Kernel file ./drivers/net/ethernet/intel/ice/ice_dpll.c — and hooo girl the family reunion is massive, so buckle up:

enum ice_dpll_pin_type(9), ice_dpll_is_sw_pin(9), ice_dpll_is_reset(9), ice_dpll_pin_freq_set(9), ice_dpll_frequency_set(9), ice_dpll_output_frequency_set(9), ice_dpll_frequency_get(9), ice_dpll_input_frequency_get(9), ice_dpll_output_frequency_get(9), ice_dpll_sw_pin_frequency_set(9), ice_dpll_sw_pin_frequency_get(9), ice_dpll_pin_enable(9), ice_dpll_pin_disable(9), ice_dpll_pin_store_state(9), ice_dpll_rclk_update_e825c(9), ice_dpll_rclk_update(9), ice_dpll_sw_pins_update(9), ice_dpll_pin_state_update(9), ice_dpll_hw_input_prio_set(9), ice_dpll_lock_status_get(9), ice_dpll_mode_get(9), ice_dpll_phase_offset_monitor_set(9), ice_dpll_phase_offset_monitor_get(9), ice_dpll_pin_state_set(9), ice_dpll_output_state_set(9), ice_dpll_input_state_set(9), ice_dpll_pin_state_get(9), ice_dpll_output_state_get(9), ice_dpll_input_state_get(9), ice_dpll_sw_pin_notify_peer(9), ice_dpll_sma_direction_set(9), ice_dpll_ufl_pin_state_set(9), ice_dpll_sw_pin_state_get(9), ice_dpll_sma_pin_state_set(9), ice_dpll_input_prio_get(9), ice_dpll_input_prio_set(9), ice_dpll_input_direction(9), ice_dpll_output_direction(9), ice_dpll_pin_sma_direction_set(9), ice_dpll_pin_sw_direction_get(9), ice_dpll_pin_phase_adjust_get(9), ice_dpll_pin_phase_adjust_set(9), ice_dpll_input_phase_adjust_set(9), ice_dpll_output_phase_adjust_set(9), ice_dpll_sw_phase_adjust_get(9), ice_dpll_sw_phase_adjust_set(9), ice_dpll_phase_offset_get(9), ice_dpll_synce_update_e825c(9), ice_dpll_output_esync_set(9), ice_dpll_output_esync_get(9), ice_dpll_input_esync_set(9), ice_dpll_input_esync_get(9), ice_dpll_sw_esync_set(9), ice_dpll_sw_esync_get(9), ice_dpll_input_ref_sync_get(9), ice_dpll_sw_input_ref_sync_get(9), ice_dpll_rclk_state_on_pin_set(9), ice_dpll_rclk_state_on_pin_get(9), ice_dpll_txclk_work(9), ice_dpll_txclk_state_on_dpll_set(9), ice_dpll_txclk_state_on_dpll_get(9), ice_generate_clock_id(9), ice_dpll_pin_ntf(9), ice_dpll_notify_changes(9), ice_dpll_is_pps_phase_monitor(9), ice_dpll_pins_notify_mask(9), ice_dpll_pps_update_phase_offsets(9), ice_dpll_update_state(9), ice_dpll_periodic_work(9), ice_dpll_init_ref_sync_inputs(9), ice_dpll_release_pins(9), ice_dpll_get_pins(9), ice_dpll_unregister_pins(9), ice_dpll_pin_ref_sync_register(9), ice_dpll_register_pins(9), ice_dpll_deinit_direct_pins(9), ice_dpll_init_direct_pins(9), ice_dpll_deinit_rclk_pin(9), ice_dpll_init_pin_common(9), ice_dpll_init_rclk_pin(9), ice_dpll_deinit_pins(9), ice_dpll_init_fwnode_pins(9), ice_dpll_init_pins_e825(9), ice_dpll_init_pins(9), ice_dpll_deinit_dpll(9), ice_dpll_init_dpll(9), ice_dpll_deinit_worker(9), ice_dpll_init_worker(9), ice_dpll_phase_range_set(9), ice_dpll_init_info_pins_generic(9), ice_dpll_init_info_direct_pins(9), ice_dpll_init_info_pin_on_pin_e825c(9), ice_dpll_init_info_rclk_pin(9), ice_dpll_init_info_sw_pins(9), ice_dpll_init_info_txclk_pins_e825c(9), ice_dpll_init_pins_info(9), ice_dpll_deinit_info(9), ice_dpll_init_info_e825c(9), ice_dpll_init_info(9), ice_dpll_deinit(9), ice_dpll_init_e825(9), ice_dpll_init_e810(9)

like I said. everyone showed up to this party 🧚✨

---

ok that's the whole page bestie, go set some frequencies (but acquire the lock first, ily) 💅

mwah 💖 this iconic little page lives in ./drivers/net/ethernet/intel/ice, dated October 2026, and answers to the name ice_dpll_inp...requency_set(9) — yes, with the dots, that's her full government name, slay 🎀