ice_dpll_input_state_set(9)

💅 ice_dpll_input_state_set(9) — from the Kernel API Manual, bestie ✨

okay so this is the whole glow-up on ice_dpll_input_state_set(9), straight outta the Kernel API Manual, and it's lowkey iconic. it flips an input pin on a dpll levice on or off. yes "levice." we keep the lore. 🎀

---

🌸 NAME 🌸

ice_dpll_input_state_set — enable/disable input pin on dpll levice 🦋

---

✨ SYNOPSIS ✨

int ice_dpll_input_state_set (const struct dpll_pin *pin , void
*pin_priv , const struct dpll_device *dpll , void *dpll_priv , enum
dpll_pin_state state , struct netlink_ext_ack *extack );

---

🫶 ARGUMENTS 🫶

• pin — pointer to a pin, bestie. it's giving "the actual thing we're touching." 💅
• pin_priv — the private data pointer that got passed on pin registration. it's been here the whole time, main character energy tbh. ✨
• dpll — the dpll being configured. the one getting the makeover. 👑
• dpll_priv — private data pointer passed on dpll registration. yes it's a whole other private pointer, no cap. 🦋
• state — state of pin to be set. this is the vibe check we're applying. 🌈
• extack — error reporting. the one who tells on you when things go sideways. 😭

---

💖 DESCRIPTION 💖

Dpll subsystem callback. Enables given mode on input type pin. literally that's it, that's the slay. 🎀

---

🔥 CONTEXT 🔥

Calls a function which acquires pf->dplls.lock. so yeah, it's out here grabbing a lock — keep that in mind before you go calling it from somewhere unhinged. 💀

---

⭐ RETURN ⭐

• 0 — successfully enabled mode. ate and left no crumbs. 🍓
• negative — failed to enable mode. not the vibe, but at least it's honest. 🙈

---

🌟 SEE ALSO 🌟

Kernel file ./drivers/net/ethernet/intel/ice/ice_dpll.c, plus enum ice_dpll_pin_type(9), ice_dpll_is_sw_pin(9), ice_dpll_is_reset(9), ice_dpll_pin_freq_set(9), ice_dpll_frequency_set(9), ice_dpll_input_frequency_set(9), ice_dpll_output_frequency_set(9), ice_dpll_frequency_get(9), ice_dpll_input_frequency_get(9), ice_dpll_output_frequency_get(9), ice_dpll_sw_pin_frequency_set(9), ice_dpll_sw_pin_frequency_get(9), ice_dpll_pin_enable(9), ice_dpll_pin_disable(9), ice_dpll_pin_store_state(9), ice_dpll_rclk_update_e825c(9), ice_dpll_rclk_update(9), ice_dpll_sw_pins_update(9), ice_dpll_pin_state_update(9), ice_dpll_hw_input_prio_set(9), ice_dpll_lock_status_get(9), ice_dpll_mode_get(9), ice_dpll_phase_offset_monitor_set(9), ice_dpll_phase_offset_monitor_get(9), ice_dpll_pin_state_set(9), ice_dpll_output_state_set(9), ice_dpll_pin_state_get(9), ice_dpll_output_state_get(9), ice_dpll_input_state_get(9), ice_dpll_sw_pin_notify_peer(9), ice_dpll_sma_direction_set(9), ice_dpll_ufl_pin_state_set(9), ice_dpll_sw_pin_state_get(9), ice_dpll_sma_pin_state_set(9), ice_dpll_input_prio_get(9), ice_dpll_input_prio_set(9), ice_dpll_input_direction(9), ice_dpll_output_direction(9), ice_dpll_pin_sma_direction_set(9), ice_dpll_pin_sw_direction_get(9), ice_dpll_pin_phase_adjust_get(9), ice_dpll_pin_phase_adjust_set(9), ice_dpll_input_phase_adjust_set(9), ice_dpll_output_phase_adjust_set(9), ice_dpll_sw_phase_adjust_get(9), ice_dpll_sw_phase_adjust_set(9), ice_dpll_phase_offset_get(9),

ice_dpll_synce_update_e825c(9), ice_dpll_output_esync_set(9), ice_dpll_output_esync_get(9), ice_dpll_input_esync_set(9), ice_dpll_input_esync_get(9), ice_dpll_sw_esync_set(9), ice_dpll_sw_esync_get(9), ice_dpll_input_ref_sync_get(9), ice_dpll_sw_input_ref_sync_get(9), ice_dpll_rclk_state_on_pin_set(9), ice_dpll_rclk_state_on_pin_get(9), ice_dpll_txclk_work(9), ice_dpll_txclk_state_on_dpll_set(9), ice_dpll_txclk_state_on_dpll_get(9), ice_generate_clock_id(9), ice_dpll_pin_ntf(9), ice_dpll_notify_changes(9), ice_dpll_is_pps_phase_monitor(9), ice_dpll_pins_notify_mask(9), ice_dpll_pps_update_phase_offsets(9), ice_dpll_update_state(9), ice_dpll_periodic_work(9), ice_dpll_init_ref_sync_inputs(9), ice_dpll_release_pins(9), ice_dpll_get_pins(9), ice_dpll_unregister_pins(9), ice_dpll_pin_ref_sync_register(9), ice_dpll_register_pins(9), ice_dpll_deinit_direct_pins(9), ice_dpll_init_direct_pins(9), ice_dpll_deinit_rclk_pin(9), ice_dpll_init_pin_common(9), ice_dpll_init_rclk_pin(9), ice_dpll_deinit_pins(9), ice_dpll_init_fwnode_pins(9), ice_dpll_init_pins_e825(9), ice_dpll_init_pins(9),

ice_dpll_deinit_dpll(9), ice_dpll_init_dpll(9), ice_dpll_deinit_worker(9), ice_dpll_init_worker(9), ice_dpll_phase_range_set(9), ice_dpll_init_info_pins_generic(9), ice_dpll_init_info_direct_pins(9), ice_dpll_init_info_pin_on_pin_e825c(9), ice_dpll_init_info_rclk_pin(9), ice_dpll_init_info_sw_pins(9), ice_dpll_init_info_txclk_pins_e825c(9), ice_dpll_init_pins_info(9), ice_dpll_deinit_info(9), ice_dpll_init_info_e825c(9), ice_dpll_init_info(9), ice_dpll_deinit(9), ice_dpll_init_e825(9), ice_dpll_init_e810(9).

---

like, that's the whole page bestie, every last reference kept intact because we do NOT skip the boring parts in this house. 💜

and for the cute lil sign-off: this all lives in ./drivers/net/ethernet/intel/ice, and it's dated October 2026 — future vibes fr fr. see u in the group chat 🫶💖🎀