ice_dpll_init_rclk_pin(9)

💅 ice_dpll_init_rclk_pin(9) — kernel API manual, bestie edition 🎀

Okay so this is a page from the Kernel API Manual, section 9, and it's all about ice_dpll_init_rclk_pin — yes the whole page, that's the vibe. Sit down, grab a strawberry drink 🍓, we're doing DPLL pins today.

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✨ NAME ✨

ice_dpll_init_rclk_pin — literally just initialize recovered clock pin 🔥 that's it, that's the whole job.

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🌸 SYNOPSIS 🌸

int ice_dpll_init_rclk_pin (struct ice_pf *pf , int start_idx , const
struct dpll_pin_ops *ops );

Three args, one int back. Iconic signature, no notes 💅

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🦋 ARGUMENTS 🦋

• pf — the board private structure 🫶 like, the whole board's personal business, okay?
• start_idx — on which index shall allocation start in the dpll subsystem. So you're telling it where to start handing out slots, periodt.
• ops — the callback ops registered with the pins 📞 the lil' functions the pins call back home with.

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👑 DESCRIPTION 👑

So what it does: it allocates a resource for the recovered clock pin in the dpll subsystem ✨ and then it registers that pin with the parents it has in the info 🌈

That's it. Allocate, register, slay. No cap.

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💀 RETURN 💀

• 0 — success 🎉 you ate
• negative — registration failure reason 😭 so if it's a negative number, something went wrong registering, and the value is the reason why

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💜 SEE ALSO 💜

Right bestie, buckle up, this list is LONG and I'm not skipping a single one — every single friend gets their name in the group chat 🫶

Kernel file ./drivers/net/ethernet/intel/ice/ice_dpll.c, plus:

enum ice_dpll_pin_type(9), ice_dpll_is_sw_pin(9), ice_dpll_is_reset(9), ice_dpll_pin_freq_set(9), ice_dpll_frequency_set(9), ice_dpll_input_frequency_set(9), ice_dpll_output_frequency_set(9), ice_dpll_frequency_get(9), ice_dpll_input_frequency_get(9), ice_dpll_output_frequency_get(9), ice_dpll_sw_pin_frequency_set(9), ice_dpll_sw_pin_frequency_get(9), ice_dpll_pin_enable(9), ice_dpll_pin_disable(9), ice_dpll_pin_store_state(9), ice_dpll_rclk_update_e825c(9), ice_dpll_rclk_update(9), ice_dpll_sw_pins_update(9), ice_dpll_pin_state_update(9), ice_dpll_hw_input_prio_set(9), ice_dpll_lock_status_get(9), ice_dpll_mode_get(9), ice_dpll_phase_offset_monitor_set(9), ice_dpll_phase_offset_monitor_get(9), ice_dpll_pin_state_set(9), ice_dpll_output_state_set(9), ice_dpll_input_state_set(9), ice_dpll_pin_state_get(9), ice_dpll_output_state_get(9), ice_dpll_input_state_get(9), ice_dpll_sw_pin_notify_peer(9), ice_dpll_sma_direction_set(9), ice_dpll_ufl_pin_state_set(9), ice_dpll_sw_pin_state_get(9), ice_dpll_sma_pin_state_set(9), ice_dpll_input_prio_get(9), ice_dpll_input_prio_set(9), ice_dpll_input_direction(9), ice_dpll_output_direction(9), ice_dpll_pin_sma_direction_set(9), ice_dpll_pin_sw_direction_get(9), ice_dpll_pin_phase_adjust_get(9), ice_dpll_pin_phase_adjust_set(9), ice_dpll_input_phase_adjust_set(9), ice_dpll_output_phase_adjust_set(9), ice_dpll_sw_phase_adjust_get(9), ice_dpll_sw_phase_adjust_set(9), ice_dpll_phase_offset_get(9), ice_dpll_synce_update_e825c(9), ice_dpll_output_esync_set(9), ice_dpll_output_esync_get(9), ice_dpll_input_esync_set(9), ice_dpll_input_esync_get(9), ice_dpll_sw_esync_set(9), ice_dpll_sw_esync_get(9), ice_dpll_input_ref_sync_get(9), ice_dpll_sw_input_ref_sync_get(9), ice_dpll_rclk_state_on_pin_set(9), ice_dpll_rclk_state_on_pin_get(9), ice_dpll_txclk_work(9), ice_dpll_txclk_state_on_dpll_set(9), ice_dpll_txclk_state_on_dpll_get(9), ice_generate_clock_id(9), ice_dpll_pin_ntf(9), ice_dpll_notify_changes(9), ice_dpll_is_pps_phase_monitor(9), ice_dpll_pins_notify_mask(9), ice_dpll_pps_update_phase_offsets(9), ice_dpll_update_state(9), ice_dpll_periodic_work(9), ice_dpll_init_ref_sync_inputs(9), ice_dpll_release_pins(9), ice_dpll_get_pins(9), ice_dpll_unregister_pins(9), ice_dpll_pin_ref_sync_register(9), ice_dpll_register_pins(9), ice_dpll_deinit_direct_pins(9), ice_dpll_init_direct_pins(9), ice_dpll_deinit_rclk_pin(9), ice_dpll_init_pin_common(9), ice_dpll_deinit_pins(9), ice_dpll_init_fwnode_pins(9), ice_dpll_init_pins_e825(9), ice_dpll_init_pins(9), ice_dpll_deinit_dpll(9), ice_dpll_init_dpll(9), ice_dpll_deinit_worker(9), ice_dpll_init_worker(9), ice_dpll_phase_range_set(9), ice_dpll_init_info_pins_generic(9), ice_dpll_init_info_direct_pins(9), ice_dpll_init_info_pin_on_pin_e825c(9), ice_dpll_init_info_rclk_pin(9), ice_dpll_init_info_sw_pins(9), ice_dpll_init_info_txclk_pins_e825c(9), ice_dpll_init_pins_info(9), ice_dpll_deinit_info(9), ice_dpll_init_info_e825c(9), ice_dpll_init_info(9), ice_dpll_deinit(9), ice_dpll_init_e825(9), ice_dpll_init_e810(9)

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💡 friendly reminder: the alloc/register behaviour above is exactly what the page says and nothing more — I'm not out here inventing extra lore, iykyk.

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Okay that's the page!! Sourced from ./drivers/net/ethernet/intel/ice, dated October 2026, manual section 9, and the whole thing is ice_dpll_init_rclk_pin(9) obviously 🌟 mwah, go register some pins bestie 💖🧚‍♀️✨