ice_dpll_input_ref_sync_get(9)

💅 ice_dpll_input_ref_sync_get(9) — the Kernel API Manual page you didn't know you needed

okay so bestie, welcome to the Kernel API Manual ✨ and today's main character is ice_dpll_input_ref_sync_get, a little callback that lives rent-free in the Intel ice driver's DPLL subsystem. she's giving "quiet achiever" energy and honestly? iconic. 🎀

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✨ NAME ✨

ice_dpll_input_ref_sync_get — callback for getting reference sync config 🦋

no cap, that's literally the whole name section. short, sweet, to the point.

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🌸 SYNOPSIS 🌸

int ice_dpll_input_ref_sync_get (const struct dpll_pin *pin , void
*pin_priv , const struct dpll_pin *ref_pin , void *ref_pin_priv , enum
dpll_pin_state *state , struct netlink_ext_ack *extack );

look at that signature. six arguments. she is thriving. 💅

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🎀 ARGUMENTS 🎀

• pin — pointer to a pin 💖 like, the pin we're talking about, okay?
• pin_priv — private data pointer passed on pin registration. yep, the private data that got handed over when the pin was registered.
• ref_pin — pin pointer for reference sync pair. it's the other half of the pair, the reference bestie 🫶
• ref_pin_priv — private data pointer of ref_pin. the reference pin's own private data, not to be confused with the first one, obviously.
• state — on success holds reference sync state for pin pair. so this is the output, the little gift she leaves you on success 🎁
• extack — error reporting. for when things go sideways, this is where the complaining happens 😭

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🔥 DESCRIPTION 🔥

so this is a Dpll subsystem callback. it's the handler for setting the reference sync frequency feature for input pin. that's the vibe. that's the whole description. periodt. 👑

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⭐ CONTEXT ⭐

this one acquires and releases pf->dplls.lock. so like, mind the lock, bestie — she takes it and gives it back, no drama, no leftovers. 🔒

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🌈 RETURN 🌈

• 0 — success 🎉 (slay)
• negative — error 💀 (not slay, but correct)

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🧚 SEE ALSO 🧚

the kernel file ./drivers/net/ethernet/intel/ice/ice_dpll.c, plus enum ice_dpll_pin_type(9), ice_dpll_is_sw_pin(9), ice_dpll_is_reset(9), ice_dpll_pin_freq_set(9), ice_dpll_frequency_set(9), ice_dpll_input_frequency_set(9), ice_dpll_output_frequency_set(9), ice_dpll_frequency_get(9), ice_dpll_input_frequency_get(9), ice_dpll_output_frequency_get(9), ice_dpll_sw_pin_frequency_set(9), ice_dpll_sw_pin_frequency_get(9), ice_dpll_pin_enable(9), ice_dpll_pin_disable(9), ice_dpll_pin_store_state(9), ice_dpll_rclk_update_e825c(9), ice_dpll_rclk_update(9), ice_dpll_sw_pins_update(9), ice_dpll_pin_state_update(9), ice_dpll_hw_input_prio_set(9), ice_dpll_lock_status_get(9), ice_dpll_mode_get(9), ice_dpll_phase_offset_monitor_set(9), ice_dpll_phase_offset_monitor_get(9), ice_dpll_pin_state_set(9), ice_dpll_output_state_set(9), ice_dpll_input_state_set(9), ice_dpll_pin_state_get(9), ice_dpll_output_state_get(9), ice_dpll_input_state_get(9), ice_dpll_sw_pin_notify_peer(9), ice_dpll_sma_direction_set(9), ice_dpll_ufl_pin_state_set(9), ice_dpll_sw_pin_state_get(9), ice_dpll_sma_pin_state_set(9), ice_dpll_input_prio_get(9), ice_dpll_input_prio_set(9), ice_dpll_input_direction(9), ice_dpll_output_direction(9), ice_dpll_pin_sma_direction_set(9), ice_dpll_pin_sw_direction_get(9), ice_dpll_pin_phase_adjust_get(9), ice_dpll_pin_phase_adjust_set(9), ice_dpll_input_phase_adjust_set(9), ice_dpll_output_phase_adjust_set(9), ice_dpll_sw_phase_adjust_get(9), ice_dpll_sw_phase_adjust_set(9), ice_dpll_phase_offset_get(9), ice_dpll_synce_update_e825c(9), ice_dpll_output_esync_set(9), ice_dpll_output_esync_get(9), ice_dpll_input_esync_set(9), ice_dpll_input_esync_get(9), ice_dpll_sw_esync_set(9), ice_dpll_sw_esync_get(9), ice_dpll_sw_input_ref_sync_get(9), ice_dpll_rclk_state_on_pin_set(9), ice_dpll_rclk_state_on_pin_get(9), ice_dpll_txclk_work(9), ice_dpll_txclk_state_on_dpll_set(9), ice_dpll_txclk_state_on_dpll_get(9), ice_generate_clock_id(9), ice_dpll_pin_ntf(9), ice_dpll_notify_changes(9), ice_dpll_is_pps_phase_monitor(9), ice_dpll_pins_notify_mask(9), ice_dpll_pps_update_phase_offsets(9), ice_dpll_update_state(9), ice_dpll_periodic_work(9), ice_dpll_init_ref_sync_inputs(9), ice_dpll_release_pins(9), ice_dpll_get_pins(9), ice_dpll_unregister_pins(9), ice_dpll_pin_ref_sync_register(9), ice_dpll_register_pins(9), ice_dpll_deinit_direct_pins(9), ice_dpll_init_direct_pins(9), ice_dpll_deinit_rclk_pin(9), ice_dpll_init_pin_common(9), ice_dpll_init_rclk_pin(9), ice_dpll_deinit_pins(9), ice_dpll_init_fwnode_pins(9), ice_dpll_init_pins_e825(9), ice_dpll_init_pins(9), ice_dpll_deinit_dpll(9), ice_dpll_init_dpll(9), ice_dpll_deinit_worker(9), ice_dpll_init_worker(9), ice_dpll_phase_range_set(9), ice_dpll_init_info_pins_generic(9), ice_dpll_init_info_direct_pins(9), ice_dpll_init_info_pin_on_pin_e825c(9), ice_dpll_init_info_rclk_pin(9), ice_dpll_init_info_sw_pins(9), ice_dpll_init_info_txclk_pins_e825c(9), ice_dpll_init_pins_info(9), ice_dpll_deinit_info(9), ice_dpll_init_info_e825c(9), ice_dpll_init_info(9), ice_dpll_deinit(9), ice_dpll_init_e825(9), ice_dpll_init_e810(9).

yeah that's a lot of cross-references. she knows everyone. iykyk 💜

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and that's the whole page, bestie — sourced from ./drivers/net/ethernet/intel/ice, dated October 2026, and published under the name ice_dpll_input_ref_sync_get(9). 🍓 go forth and get that reference sync config, you gorgeous nerd. 💖✨