ice_dpll_sw_esync_set(9)

📦 version 7.3.1, in nixpkgs unstable

💅 ice_dpll_sw_esync_set — NAME ✨

okay so bestie, this page is from the Kernel API Manual, and the function we're simping over is ice_dpll_sw_esync_set — literally the callback for setting embedded sync on an SW pin. that's it, that's the whole vibe. 🎀

🌸 SYNOPSIS 🌸

int ice_dpll_sw_esync_set (const struct dpll_pin *pin , void *pin_priv ,
const struct dpll_device *dpll , void *dpll_priv , u64 freq , struct
netlink_ext_ack *extack );

🦋 ARGUMENTS 🦋

like, six whole parameters. she's got range. 💅

  • pin — pointer to a pin. just a lil pointer, living her life 🫶
  • pin_priv — the private data pointer that got passed on pin registration. so like, her personal stash ✨
  • dpll — the registered dpll pointer. the main character honestly 👑
  • dpll_priv — private data pointer passed on dpll registration. the dpll's own little bag of secrets 🙈
  • freq — the requested embedded sync frequency, as a u64. the number that matters ⭐
  • extack — error reporting. she's the one who tells you when things went sideways 😭

💜 DESCRIPTION 💜

this is a Dpll subsystem callback — a handler for setting the embedded sync frequency value on an SW pin. no cap, that's literally her job. you want the embedded sync frequency set on that software pin? she's the one you call. periodt. 🔥

🌈 CONTEXT 🌈

heads up bestie: she calls a function which acquires and releases pf->dplls.lock. so like, the lock gets taken and given back. don't be weird about it, the function handles it. 💀

⭐ RETURN ⭐

  • 0 — success. slay, it worked 💖
  • negative — error. not slay, but informative 😭

🧚 SEE ALSO 🧚

okay buckle up because this list is long — it's giving "she knows everyone at the function." every single one of these, coming right up:

the kernel file itself & the pin-type enum:

  • ./drivers/net/ethernet/intel/ice/ice_dpll.c
  • enum ice_dpll_pin_type(9)

pin checks & frequency stuff:

enable / disable / state storage:

rclk & sw pin updates:

prio, lock status, mode:

phase offset monitors:

all the state setters:

all the state getters:

sma & ufl energy:

input prio, directions:

phase adjust squad:

synce:

esync everything (her siblings 💖):

ref sync:

rclk state on pin:

txclk crew:

clock id & notifications:

init & registration era:

direct pin init/deinit:

rclk pin init/deinit:

pin init/deinit overall:

dpll init/deinit:

worker init/deinit:

phase range:

info init squad:

top-level init/deinit:

and that's the whole page bestie, ily, go set some embedded sync 💖

little sign-off from the source: this one lives in ./drivers/net/ethernet/intel/ice, and it's dated October 2026. bookmark it, it's iconic ✨🦋🎀
📦 where this page comes from