ice_dpll_is_sw_pin(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ‘‘ ice_dpll_is_sw_pin β€” the "wait, is this pin ours to touch?" checker πŸ’…

okay bestie so real quick, we're in the Kernel API Manual today and this is genuinely one of the cutest little helpers in ice_dpll β€” it's just a yes/no vibe check on a pin, no cap ✨


🌸 SYNOPSIS 🌸

bool ice_dpll_is_sw_pin (struct ice_pf *pf , u8 index , bool input );

πŸŽ€ ARGUMENTS πŸŽ€

  • pf β€” the private board structure πŸ’– like, your whole NIC's little diary
  • index β€” the index of a pin, "as understood by FW" β€” so like the firmware's own numbering, don't @ me with your own scheme πŸ™ˆ
  • input β€” true for input, false for output. literally that simple πŸ¦‹

✨ DESCRIPTION ✨

So what this does is check whether the pin shall be controlled by SW β€” instead of just handing out raw access for pin control. 🫢

Now here's the tea for E810 NIC with dpll: there's extra MUX-related logic sitting between the SMA/U.FL pins/connectors and the dpll device. 😭 It's giving tangled. So the move β€” the iconic move β€” is to give the user access through a series of wrapper functions, because from the user's perspective those wrappers convey a single functionality rather than a bunch of separated pins. periodt πŸ’…


🌈 RETURN 🌈

  • true β€” pin controlled by SW πŸ”₯ slay
  • false β€” pin not controlled by SW πŸ’€ not it

πŸ’œ SEE ALSO πŸ’œ

Kernel file ./drivers/net/ethernet/intel/ice/ice_dpll.c β€” and bestie, buckle up, the friend group is huge: enum ice_dpll_pin_type(9), ice_dpll_is_reset(9), ice_dpll_pin_freq_set(9), ice_dpll_frequency_set(9), ice_dpll_input_frequency_set(9), ice_dpll_output_frequency_set(9), ice_dpll_frequency_get(9), ice_dpll_input_frequency_get(9), ice_dpll_output_frequency_get(9), ice_dpll_sw_pin_frequency_set(9), ice_dpll_sw_pin_frequency_get(9), ice_dpll_pin_enable(9), ice_dpll_pin_disable(9), ice_dpll_pin_store_state(9), ice_dpll_rclk_update_e825c(9), ice_dpll_rclk_update(9), ice_dpll_sw_pins_update(9), ice_dpll_pin_state_update(9), ice_dpll_hw_input_prio_set(9), ice_dpll_lock_status_get(9), ice_dpll_mode_get(9), ice_dpll_phase_offset_monitor_set(9), ice_dpll_phase_offset_monitor_get(9), ice_dpll_pin_state_set(9), ice_dpll_output_state_set(9), ice_dpll_input_state_set(9), ice_dpll_pin_state_get(9), ice_dpll_output_state_get(9), ice_dpll_input_state_get(9), ice_dpll_sw_pin_notify_peer(9), ice_dpll_sma_direction_set(9), ice_dpll_ufl_pin_state_set(9), ice_dpll_sw_pin_state_get(9), ice_dpll_sma_pin_state_set(9), ice_dpll_input_prio_get(9), ice_dpll_input_prio_set(9), ice_dpll_input_direction(9), ice_dpll_output_direction(9), ice_dpll_pin_sma_direction_set(9), ice_dpll_pin_sw_direction_get(9), ice_dpll_pin_phase_adjust_get(9), ice_dpll_pin_phase_adjust_set(9), ice_dpll_input_phase_adjust_set(9), ice_dpll_output_phase_adjust_set(9), ice_dpll_sw_phase_adjust_get(9), ice_dpll_sw_phase_adjust_set(9), ice_dpll_phase_offset_get(9), ice_dpll_synce_update_e825c(9), ice_dpll_output_esync_set(9), ice_dpll_output_esync_get(9), ice_dpll_input_esync_set(9), ice_dpll_input_esync_get(9), ice_dpll_sw_esync_set(9), ice_dpll_sw_esync_get(9), ice_dpll_input_ref_sync_get(9), ice_dpll_sw_input_ref_sync_get(9), ice_dpll_rclk_state_on_pin_set(9), ice_dpll_rclk_state_on_pin_get(9), ice_dpll_txclk_work(9), ice_dpll_txclk_state_on_dpll_set(9), ice_dpll_txclk_state_on_dpll_get(9), ice_generate_clock_id(9), ice_dpll_pin_ntf(9), ice_dpll_notify_changes(9), ice_dpll_is_pps_phase_monitor(9), ice_dpll_pins_notify_mask(9), ice_dpll_pps_update_phase_offsets(9), ice_dpll_update_state(9), ice_dpll_periodic_work(9), ice_dpll_init_ref_sync_inputs(9), ice_dpll_release_pins(9), ice_dpll_get_pins(9), ice_dpll_unregister_pins(9), ice_dpll_pin_ref_sync_register(9), ice_dpll_register_pins(9), ice_dpll_deinit_direct_pins(9), ice_dpll_init_direct_pins(9), ice_dpll_deinit_rclk_pin(9), ice_dpll_init_pin_common(9), ice_dpll_init_rclk_pin(9), ice_dpll_deinit_pins(9), ice_dpll_init_fwnode_pins(9), ice_dpll_init_pins_e825(9), ice_dpll_init_pins(9), ice_dpll_deinit_dpll(9), ice_dpll_init_dpll(9), ice_dpll_deinit_worker(9), ice_dpll_init_worker(9), ice_dpll_phase_range_set(9), ice_dpll_init_info_pins_generic(9), ice_dpll_init_info_direct_pins(9), ice_dpll_init_info_pin_on_pin_e825c(9), ice_dpll_init_info_rclk_pin(9), ice_dpll_init_info_sw_pins(9), ice_dpll_init_info_txclk_pins_e825c(9), ice_dpll_init_pins_info(9), ice_dpll_deinit_info(9), ice_dpll_init_info_e825c(9), ice_dpll_init_info(9), ice_dpll_deinit(9), ice_dpll_init_e825(9), ice_dpll_init_e810(9) 🌟


ngl bestie, if you made it through that whole SEE ALSO list you deserve a little treat πŸ“ iykyk

and that's the whole page!! brought to you straight outta ./drivers/net/ethernet/intel/ice, stamped October 2026 πŸŽ€ go forth and check those pins, main character πŸ’–πŸ¦‹

πŸ“¦ where this page comes from