ice_dpll_frequency_set(9)
π
ice_dpll_frequency_set β the Kernel API Manual tea π
okay bestie, so this page is literally ice_dpll_frequency_set(9) from the Kernel API Manual, and it's way less scary than the name makes it sound, i'm so serious. it's a little wrapper function, a middle-man, a hype-friend for the pin callback. let's get into it β¨
πΈ NAME πΈ
ice_dpll_frequency_set β the wrapper for the pin callback for set frequency. that's it, that's the whole vibe π«Ά
β¨ SYNOPSIS β¨
int ice_dpll_frequency_set (const struct dpll_pin *pin , void *pin_priv
, const struct dpll_device *dpll , void *dpll_priv , const u32 frequency
, struct netlink_ext_ack *extack , enum ice_dpll_pin_type pin_type );
like, seven whole arguments, she's high-maintenance but she delivers π
π¦ ARGUMENTS π¦
pinβ a pointer to a pin. just. a pin. pointing at it πpin_privβ the private data pointer that got passed on pin registration (you gave it to her earlier, she remembers)dpllβ a pointer to dplldpll_privβ the private data pointer that got passed on dpll registration (same energy, different registration)frequencyβ the frequency to be set. the whole point, honestly πextackβ error reporting, aka the receipts when something goes wrong π§Ύpin_typeβ the type of pin being configured, because not all pins are the same and we respect that π
π₯ DESCRIPTION π₯
so what does she actually do? she wraps the internal set frequency command on a pin. that's the gig. a tidy little wrapper, a cozy lil intermediary, no cap. she takes your args and she makes the frequency-setting happen through the proper channel πβ¨
π CONTEXT π
bestie, listen β this one acquires pf->dplls.lock. she's locking. respect the lock. ππ
β RETURN β
0β success! we ate, we slayed, the frequency is set π π- negative β error, specifically: pin not found or it couldn't set in hw ππ (not her fault, ok, she tried)
π SEE ALSO π
okay this is the part where she tags literally everyone in the group chat. grab a snack, this list is long π
- Kernel file
./drivers/net/ethernet/intel/ice/ice_dpll.cenumice_dpll_pin_type(9) ice_dpll_is_sw_pin(9)ice_dpll_is_reset(9)ice_dpll_pin_freq_set(9)ice_dpll_input_frequency_set(9)ice_dpll_output_frequency_set(9)ice_dpll_frequency_get(9)ice_dpll_input_frequency_get(9)ice_dpll_output_frequency_get(9)ice_dpll_sw_pin_frequency_set(9)ice_dpll_sw_pin_frequency_get(9)ice_dpll_pin_enable(9)ice_dpll_pin_disable(9)ice_dpll_pin_store_state(9)ice_dpll_rclk_update_e825c(9)ice_dpll_rclk_update(9)ice_dpll_sw_pins_update(9)ice_dpll_pin_state_update(9)ice_dpll_hw_input_prio_set(9)ice_dpll_lock_status_get(9)ice_dpll_mode_get(9)ice_dpll_phase_offset_monitor_set(9)ice_dpll_phase_offset_monitor_get(9)ice_dpll_pin_state_set(9)ice_dpll_output_state_set(9)ice_dpll_input_state_set(9)ice_dpll_pin_state_get(9)ice_dpll_output_state_get(9)ice_dpll_input_state_get(9)ice_dpll_sw_pin_notify_peer(9)ice_dpll_sma_direction_set(9)ice_dpll_ufl_pin_state_set(9)ice_dpll_sw_pin_state_get(9)ice_dpll_sma_pin_state_set(9)ice_dpll_input_prio_get(9)ice_dpll_input_prio_set(9)ice_dpll_input_direction(9)ice_dpll_output_direction(9)ice_dpll_pin_sma_direction_set(9)ice_dpll_pin_sw_direction_get(9)ice_dpll_pin_phase_adjust_get(9)ice_dpll_pin_phase_adjust_set(9)ice_dpll_input_phase_adjust_set(9)ice_dpll_output_phase_adjust_set(9)ice_dpll_sw_phase_adjust_get(9)ice_dpll_sw_phase_adjust_set(9)ice_dpll_phase_offset_get(9)ice_dpll_synce_update_e825c(9)ice_dpll_output_esync_set(9)ice_dpll_output_esync_get(9)ice_dpll_input_esync_set(9)ice_dpll_input_esync_get(9)ice_dpll_sw_esync_set(9)ice_dpll_sw_esync_get(9)ice_dpll_input_ref_sync_get(9)ice_dpll_sw_input_ref_sync_get(9)ice_dpll_rclk_state_on_pin_set(9)ice_dpll_rclk_state_on_pin_get(9)ice_dpll_txclk_work(9)ice_dpll_txclk_state_on_dpll_set(9)ice_dpll_txclk_state_on_dpll_get(9)ice_generate_clock_id(9)ice_dpll_pin_ntf(9)ice_dpll_notify_changes(9)ice_dpll_is_pps_phase_monitor(9)ice_dpll_pins_notify_mask(9)ice_dpll_pps_update_phase_offsets(9)ice_dpll_update_state(9)ice_dpll_periodic_work(9)ice_dpll_init_ref_sync_inputs(9)ice_dpll_release_pins(9)ice_dpll_get_pins(9)ice_dpll_unregister_pins(9)ice_dpll_pin_ref_sync_register(9)ice_dpll_register_pins(9)ice_dpll_deinit_direct_pins(9)ice_dpll_init_direct_pins(9)ice_dpll_deinit_rclk_pin(9)ice_dpll_init_pin_common(9)ice_dpll_init_rclk_pin(9)ice_dpll_deinit_pins(9)ice_dpll_init_fwnode_pins(9)ice_dpll_init_pins_e825(9)ice_dpll_init_pins(9)ice_dpll_deinit_dpll(9)ice_dpll_init_dpll(9)ice_dpll_deinit_worker(9)ice_dpll_init_worker(9)ice_dpll_phase_range_set(9)ice_dpll_init_info_pins_generic(9)ice_dpll_init_info_direct_pins(9)ice_dpll_init_info_pin_on_pin_e825c(9)ice_dpll_init_info_rclk_pin(9)ice_dpll_init_info_sw_pins(9)ice_dpll_init_info_txclk_pins_e825c(9)ice_dpll_init_pins_info(9)ice_dpll_deinit_info(9)ice_dpll_init_info_e825c(9)ice_dpll_init_info(9)ice_dpll_deinit(9)ice_dpll_init_e825(9)ice_dpll_init_e810(9)
and that's the whole page bestie, you're officially educated π§π
ngl the "wrapper for a wrapper" pipeline is giving main character energy of the supporting cast, but we respect her. she locks, she sets frequency, she leaves. periodt. π
sign-off time π«Ά: this lil gem lives in ./drivers/net/ethernet/intel/ice and it's dated October 2026 β yeah, future vibes, we stay ahead of the timeline βπΈ
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms