ice_dpll_input_esync_get(9)

💅 ice_dpll_input_esync_get — a Kernel API Manual moment

okay so bestie, welcome to the glow-up of ice_dpll_input_esync_get(9) from the Kernel API Manual ✨ this one's a little callback that goes and fetches your embedded sync config, and honestly? it's giving main character energy in the DPLL subsystem 🎀

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✨ NAME ✨

ice_dpll_input_esync_get — the callback for getting embedded sync config 🦋

🌸 SYNOPSIS 🌸

int ice_dpll_input_esync_get (const struct dpll_pin *pin , void
*pin_priv , const struct dpll_device *dpll , void *dpll_priv , struct
dpll_pin_esync *esync , struct netlink_ext_ack *extack );

💖 ARGUMENTS 💖

• pin — pointer to a pin 📍 literally just pointing at your pin, bestie
• pin_priv — private data pointer passed on pin registration 🙈 the little secret handshake your pin got at registration
• dpll — registered dpll pointer 👑 the dpll that's already registered, front and center
• dpll_priv — private data pointer passed on dpll registration 🫶 same deal, but this time the private data your dpll handed over when it registered
• esync — on success holds embedded sync pin properties ✨ if everything slays, this is where the embedded sync pin properties live
• extack — error reporting 😭 the messenger when things go sideways

🦋 DESCRIPTION 🦋

so this is a Dpll subsystem callback 🌈 — no cap. It's the handler for getting the embedded sync frequency value and capabilities on an input pin. That's the whole vibe. It handles the getting of the esync frequency value and the capabilities, on an input pin, periodt 💅

🔥 CONTEXT 🔥

Acquires pf->dplls.lock 🔒 — yes queen, it takes the lock. Don't be weird about it.

⭐ RETURN ⭐

• 0 — success 🎉 ate, no crumbs
• negative — error 💀 yeah that's the whole other option

👑 SEE ALSO 👑

The kernel file lives at ./drivers/net/ethernet/intel/ice/ice_dpll.c 🧚 and honestly the friend group here is huge, so buckle up:

enum ice_dpll_pin_type(9), ice_dpll_is_sw_pin(9), ice_dpll_is_reset(9), ice_dpll_pin_freq_set(9), ice_dpll_frequency_set(9), ice_dpll_input_frequency_set(9), ice_dpll_output_frequency_set(9), ice_dpll_frequency_get(9), ice_dpll_input_frequency_get(9), ice_dpll_output_frequency_get(9), ice_dpll_sw_pin_frequency_set(9), ice_dpll_sw_pin_frequency_get(9), ice_dpll_pin_enable(9), ice_dpll_pin_disable(9), ice_dpll_pin_store_state(9), ice_dpll_rclk_update_e825c(9), ice_dpll_rclk_update(9), ice_dpll_sw_pins_update(9), ice_dpll_pin_state_update(9), ice_dpll_hw_input_prio_set(9), ice_dpll_lock_status_get(9), ice_dpll_mode_get(9), ice_dpll_phase_offset_monitor_set(9), ice_dpll_phase_offset_monitor_get(9), ice_dpll_pin_state_set(9), ice_dpll_output_state_set(9), ice_dpll_input_state_set(9), ice_dpll_pin_state_get(9), ice_dpll_output_state_get(9), ice_dpll_input_state_get(9), ice_dpll_sw_pin_notify_peer(9), ice_dpll_sma_direction_set(9), ice_dpll_ufl_pin_state_set(9), ice_dpll_sw_pin_state_get(9), ice_dpll_sma_pin_state_set(9), ice_dpll_input_prio_get(9), ice_dpll_input_prio_set(9), ice_dpll_input_direction(9), ice_dpll_output_direction(9), ice_dpll_pin_sma_direction_set(9), ice_dpll_pin_sw_direction_get(9), ice_dpll_pin_phase_adjust_get(9), ice_dpll_pin_phase_adjust_set(9), ice_dpll_input_phase_adjust_set(9), ice_dpll_output_phase_adjust_set(9), ice_dpll_sw_phase_adjust_get(9), ice_dpll_sw_phase_adjust_set(9), ice_dpll_phase_offset_get(9), ice_dpll_synce_update_e825c(9), ice_dpll_output_esync_set(9), ice_dpll_output_esync_get(9), ice_dpll_input_esync_set(9), ice_dpll_sw_esync_set(9), ice_dpll_sw_esync_get(9), ice_dpll_input_ref_sync_get(9), ice_dpll_sw_input_ref_sync_get(9), ice_dpll_rclk_state_on_pin_set(9), ice_dpll_rclk_state_on_pin_get(9), ice_dpll_txclk_work(9), ice_dpll_txclk_state_on_dpll_set(9), ice_dpll_txclk_state_on_dpll_get(9), ice_generate_clock_id(9), ice_dpll_pin_ntf(9), ice_dpll_notify_changes(9), ice_dpll_is_pps_phase_monitor(9), ice_dpll_pins_notify_mask(9), ice_dpll_pps_update_phase_offsets(9), ice_dpll_update_state(9), ice_dpll_periodic_work(9), ice_dpll_init_ref_sync_inputs(9), ice_dpll_release_pins(9), ice_dpll_get_pins(9), ice_dpll_unregister_pins(9), ice_dpll_pin_ref_sync_register(9), ice_dpll_register_pins(9), ice_dpll_deinit_direct_pins(9), ice_dpll_init_direct_pins(9), ice_dpll_deinit_rclk_pin(9), ice_dpll_init_pin_common(9), ice_dpll_init_rclk_pin(9), ice_dpll_deinit_pins(9), ice_dpll_init_fwnode_pins(9), ice_dpll_init_pins_e825(9), ice_dpll_init_pins(9), ice_dpll_deinit_dpll(9), ice_dpll_init_dpll(9), ice_dpll_deinit_worker(9), ice_dpll_init_worker(9), ice_dpll_phase_range_set(9), ice_dpll_init_info_pins_generic(9), ice_dpll_init_info_direct_pins(9), ice_dpll_init_info_pin_on_pin_e825c(9), ice_dpll_init_info_rclk_pin(9), ice_dpll_init_info_sw_pins(9), ice_dpll_init_info_txclk_pins_e825c(9), ice_dpll_init_pins_info(9), ice_dpll_deinit_info(9), ice_dpll_init_info_e825c(9), ice_dpll_init_info(9), ice_dpll_deinit(9), ice_dpll_init_e825(9), ice_dpll_init_e810(9)

and separately, the directory ./drivers/net/ethernet/intel/ice 🌸

ngl bestie that's a lot of siblings but they're all iconic in their own way 💜

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okay that's the whole page!! 🎀 dropping the credits: this one came from ./drivers/net/ethernet/intel/ice, and it's dated October 2026 — iykyk 💅✨ mwah, go read the source, ilysm 🫶💖