ice_dpll_pi...e_adjust_set(9)
π NAME π
okay so bestie, welcome to the Kernel API Manual entry for ice_dpll_pi...e_adjust_set(9) β yeah the page title got a lil truncated, it's fine, we move π β and this one is literally just a helper for setting a pin phase adjust value. That's the whole vibe. π
β¨ SYNOPSIS β¨
int ice_dpll_pin_phase_adjust_set (const struct dpll_pin *pin , void
*pin_priv , const struct dpll_device *dpll , void *dpll_priv , s32
phase_adjust , struct netlink_ext_ack *extack , enum ice_dpll_pin_type
type );
π«Ά ARGUMENTS π«Ά
seven (7) whole args, she's thorough, we respect it:
pinβ pointer to a pin π§ like, the actual pin object, hi bestiepin_privβ private data pointer that was passed on pin registration (you handed it over at registration, now it comes back to you, iykyk)dpllβ the registered dpll pointer πdpll_privβ private data pointer passed on dpll registration, same deal as above but for the dpllphase_adjustβ the phase_adjust to be set, which is genuinely the most self-explanatory argument on this entire page nglextackβ error reporting π£ (this is where the complaints go)typeβ type of a pin, no cap, it's anenum ice_dpll_pin_type
π DESCRIPTION π
So this is a helper for a dpll subsystem callback β it's the handler for setting the phase adjust value of a pin. That's it, that's the whole job, and honestly? She ate. β¨
π CONTEXT π
Acquires pf->dplls.lock β yes bestie, there is a lock, this function is not out here rawdogging concurrency, we love a responsible icon. π«Ά
π RETURN π
0β success π slay- negative β error π (something went off, go check
extack)
π¦ SEE ALSO π¦
okay this list is LONG long, buckle up, she's thorough and we're not skipping a single one, periodt. First up, housekeeping: the kernel file is ./drivers/net/ethernet/intel/ice/ice_dpll.c, and it points you at enum ice_dpll_pin_type(9). Then the whole ensemble cast:
ice_dpll_is_sw_pin(9)ice_dpll_is_reset(9)ice_dpll_pin_freq_set(9)ice_dpll_frequency_set(9)ice_dpll_input_frequency_set(9)ice_dpll_output_frequency_set(9)ice_dpll_frequency_get(9)ice_dpll_input_frequency_get(9)ice_dpll_output_frequency_get(9)ice_dpll_sw_pin_frequency_set(9)ice_dpll_sw_pin_frequency_get(9)ice_dpll_pin_enable(9)ice_dpll_pin_disable(9)ice_dpll_pin_store_state(9)ice_dpll_rclk_update_e825c(9)ice_dpll_rclk_update(9)ice_dpll_sw_pins_update(9)ice_dpll_pin_state_update(9)ice_dpll_hw_input_prio_set(9)ice_dpll_lock_status_get(9)ice_dpll_mode_get(9)ice_dpll_phase_offset_monitor_set(9)ice_dpll_phase_offset_monitor_get(9)ice_dpll_pin_state_set(9)ice_dpll_output_state_set(9)ice_dpll_input_state_set(9)ice_dpll_pin_state_get(9)ice_dpll_output_state_get(9)ice_dpll_input_state_get(9)ice_dpll_sw_pin_notify_peer(9)ice_dpll_sma_direction_set(9)ice_dpll_ufl_pin_state_set(9)ice_dpll_sw_pin_state_get(9)ice_dpll_sma_pin_state_set(9)ice_dpll_input_prio_get(9)ice_dpll_input_prio_set(9)ice_dpll_input_direction(9)ice_dpll_output_direction(9)ice_dpll_pin_sma_direction_set(9)ice_dpll_pin_sw_direction_get(9)ice_dpll_pin_phase_adjust_get(9)ice_dpll_input_phase_adjust_set(9)ice_dpll_output_phase_adjust_set(9)ice_dpll_sw_phase_adjust_get(9)ice_dpll_sw_phase_adjust_set(9)ice_dpll_phase_offset_get(9)ice_dpll_synce_update_e825c(9)ice_dpll_output_esync_set(9)ice_dpll_output_esync_get(9)ice_dpll_input_esync_set(9)ice_dpll_input_esync_get(9)ice_dpll_sw_esync_set(9)ice_dpll_sw_esync_get(9)ice_dpll_input_ref_sync_get(9)ice_dpll_sw_input_ref_sync_get(9)ice_dpll_rclk_state_on_pin_set(9)ice_dpll_rclk_state_on_pin_get(9)ice_dpll_txclk_work(9)ice_dpll_txclk_state_on_dpll_set(9)ice_dpll_txclk_state_on_dpll_get(9)ice_generate_clock_id(9)ice_dpll_pin_ntf(9)ice_dpll_notify_changes(9)ice_dpll_is_pps_phase_monitor(9)ice_dpll_pins_notify_mask(9)ice_dpll_pps_update_phase_offsets(9)ice_dpll_update_state(9)ice_dpll_periodic_work(9)ice_dpll_init_ref_sync_inputs(9)ice_dpll_release_pins(9)ice_dpll_get_pins(9)ice_dpll_unregister_pins(9)ice_dpll_pin_ref_sync_register(9)ice_dpll_register_pins(9)ice_dpll_deinit_direct_pins(9)ice_dpll_init_direct_pins(9)ice_dpll_deinit_rclk_pin(9)ice_dpll_init_pin_common(9)ice_dpll_init_rclk_pin(9)ice_dpll_deinit_pins(9)ice_dpll_init_fwnode_pins(9)ice_dpll_init_pins_e825(9)ice_dpll_init_pins(9)ice_dpll_deinit_dpll(9)ice_dpll_init_dpll(9)ice_dpll_deinit_worker(9)ice_dpll_init_worker(9)ice_dpll_phase_range_set(9)ice_dpll_init_info_pins_generic(9)ice_dpll_init_info_direct_pins(9)ice_dpll_init_info_pin_on_pin_e825c(9)ice_dpll_init_info_rclk_pin(9)ice_dpll_init_info_sw_pins(9)ice_dpll_init_info_txclk_pins_e825c(9)ice_dpll_init_pins_info(9)ice_dpll_deinit_info(9)ice_dpll_init_info_e825c(9)ice_dpll_init_info(9)ice_dpll_deinit(9)ice_dpll_init_e825(9)ice_dpll_init_e810(9)
like I said. long. but we got there together π«Ά
and that's the page, bestie β brought to you from ./drivers/net/ethernet/intel/ice, dated October 2026. go set some phase adjusts, ily, bye πβ¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms