ice_dpll_init_direct_pins(9)
π
ice_dpll_init_direct_pins β Kernel API Manual, bestie edition
okay so bestie. this is ice_dpll_init_direct_pins(9) from the Kernel API Manual, and it is literally the glow-up function for the Intel ice driver's DPLL pins. she's giving "make the direct pins exist in the dpll subsystem" main character energy and we're gonna walk through her whole vibe. π
β¨ NAME
ice_dpll_init_direct_pins β initialize direct pins π
like, that's it. that's the whole job. initialize. direct pins. slay.
π¦ SYNOPSIS
int ice_dpll_init_direct_pins (struct ice_pf *pf , bool cgu , struct
ice_dpll_pin *pins , int start_idx , int count , const struct
dpll_pin_ops *ops , struct dpll_device *first , struct dpll_device
*second );
eight whole arguments, no cap. she's high-maintenance but worth it. π₯
πΈ ARGUMENTS
pfβ board private structure. the NIC's personal diary, basically π«Άcguβ ifcguis present and controlled by this NIC. yes/no energy πpinsβ pointer to the pins array. the whole friend group πstart_idxβ on which index shall allocation start in dpll subsystem πcountβ number of pins. how many besties we bringing β¨opsβ callback ops registered with the pins. the little behavior menu πfirstβ dpll device pointer πsecondβ dpll device pointer (yes, a second one. she has two hands π«Άπ«Ά)
π DESCRIPTION
okay so here's the tea. she allocates directly connected pins of a given array in the dpll subsystem. that's the whole assignment, no notes. π
and if cgu is owned, she registers the allocated pins with the given dplls. that's it. that's the function. iykyk. π§
π RETURN
- β
0β success. ate. π₯ - β negative β registration failure reason. not slay, but at least she tells you why π
β SEE ALSO
okay bestie this list is long long, so buckle up, we're going shopping ποΈ β starting with the kernel file herself:
./drivers/net/ethernet/intel/ice/ice_dpll.cenum ice_dpll_pin_type(9)ice_dpll_is_sw_pin(9)ice_dpll_is_reset(9)ice_dpll_pin_freq_set(9)ice_dpll_frequency_set(9)ice_dpll_input_frequency_set(9)ice_dpll_output_frequency_set(9)ice_dpll_frequency_get(9)ice_dpll_input_frequency_get(9)ice_dpll_output_frequency_get(9)ice_dpll_sw_pin_frequency_set(9)ice_dpll_sw_pin_frequency_get(9)ice_dpll_pin_enable(9)ice_dpll_pin_disable(9)ice_dpll_pin_store_state(9)ice_dpll_rclk_update_e825c(9)ice_dpll_rclk_update(9)ice_dpll_sw_pins_update(9)ice_dpll_pin_state_update(9)ice_dpll_hw_input_prio_set(9)ice_dpll_lock_status_get(9)ice_dpll_mode_get(9)ice_dpll_phase_offset_monitor_set(9)ice_dpll_phase_offset_monitor_get(9)ice_dpll_pin_state_set(9)ice_dpll_output_state_set(9)ice_dpll_input_state_set(9)ice_dpll_pin_state_get(9)ice_dpll_output_state_get(9)ice_dpll_input_state_get(9)ice_dpll_sw_pin_notify_peer(9)ice_dpll_sma_direction_set(9)ice_dpll_ufl_pin_state_set(9)ice_dpll_sw_pin_state_get(9)ice_dpll_sma_pin_state_set(9)ice_dpll_input_prio_get(9)ice_dpll_input_prio_set(9)ice_dpll_input_direction(9)ice_dpll_output_direction(9)ice_dpll_pin_sma_direction_set(9)ice_dpll_pin_sw_direction_get(9)ice_dpll_pin_phase_adjust_get(9)ice_dpll_pin_phase_adjust_set(9)ice_dpll_input_phase_adjust_set(9)ice_dpll_output_phase_adjust_set(9)ice_dpll_sw_phase_adjust_get(9)ice_dpll_sw_phase_adjust_set(9)ice_dpll_phase_offset_get(9)ice_dpll_synce_update_e825c(9)ice_dpll_output_esync_set(9)ice_dpll_output_esync_get(9)ice_dpll_input_esync_set(9)ice_dpll_input_esync_get(9)ice_dpll_sw_esync_set(9)ice_dpll_sw_esync_get(9)ice_dpll_input_ref_sync_get(9)ice_dpll_sw_input_ref_sync_get(9)ice_dpll_rclk_state_on_pin_set(9)ice_dpll_rclk_state_on_pin_get(9)ice_dpll_txclk_work(9)ice_dpll_txclk_state_on_dpll_set(9)ice_dpll_txclk_state_on_dpll_get(9)ice_generate_clock_id(9)ice_dpll_pin_ntf(9)ice_dpll_notify_changes(9)ice_dpll_is_pps_phase_monitor(9)ice_dpll_pins_notify_mask(9)ice_dpll_pps_update_phase_offsets(9)ice_dpll_update_state(9)ice_dpll_periodic_work(9)ice_dpll_init_ref_sync_inputs(9)ice_dpll_release_pins(9)ice_dpll_get_pins(9)ice_dpll_unregister_pins(9)ice_dpll_pin_ref_sync_register(9)ice_dpll_register_pins(9)ice_dpll_deinit_direct_pins(9)ice_dpll_deinit_rclk_pin(9)ice_dpll_init_pin_common(9)ice_dpll_init_rclk_pin(9)ice_dpll_deinit_pins(9)ice_dpll_init_fwnode_pins(9)ice_dpll_init_pins_e825(9)ice_dpll_init_pins(9)ice_dpll_deinit_dpll(9)ice_dpll_init_dpll(9)ice_dpll_deinit_worker(9)ice_dpll_init_worker(9)ice_dpll_phase_range_set(9)ice_dpll_init_info_pins_generic(9)ice_dpll_init_info_direct_pins(9)ice_dpll_init_info_pin_on_pin_e825c(9)ice_dpll_init_info_rclk_pin(9)ice_dpll_init_info_sw_pins(9)ice_dpll_init_info_txclk_pins_e825c(9)ice_dpll_init_pins_info(9)ice_dpll_deinit_info(9)ice_dpll_init_info_e825c(9)ice_dpll_init_info(9)ice_dpll_deinit(9)ice_dpll_init_e825(9)ice_dpll_init_e810(9)
bestie that was a lot of cross-references and we got through all of them together. proud of us fr fr π«Ά
and that's the page!! π¦ this whole thing lives in ./drivers/net/ethernet/intel/ice and it's dated October 2026 β iconic, timeless, periodt. go read some kernel source and hydrate, ily πβ¨π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms