ice_dpll_hw_input_prio_set(9)
π
ice_dpll_hw_input_prio_set β like, the Kernel API Manual page, bestie π
okay so picture this: you're deep in the kernel, you've got a DPLL, you've got pins, and you need the hardware itself to know which input actually matters. That's this function. Welcome to the Kernel API Manual entry for ice_dpll_hw_input_prio_set(9) β buckle up, it's giving "small function, big responsibilities" β¨
πΈ NAME πΈ
ice_dpll_hw_input_prio_set β set the input priority value in hardware π no cap, that's literally the whole job.
β SYNOPSIS β
int ice_dpll_hw_input_prio_set (struct ice_pf *pf , struct ice_dpll
*dpll , struct ice_dpll_pin *pin , const u32 prio , struct
netlink_ext_ack *extack );
π¦ ARGUMENTS π¦
pfβ the board private structure π«Ά your whole device's personal lore lives in heredpllβ the ice dpll pointer π« yes, that dpllpinβ the ice pin pointer π the specific pin we're doing this toprioβ the priority value being set on a dpll π aconst u32, so treat it with respectextackβ error reporting π because when things go wrong, someone's gotta tell the netlink girlies about it
π DESCRIPTION π
It's an internal wrapper for setting the priority in the hardware. That's it, that's the vibe β a neat little internal wrapper so the rest of the driver doesn't have to rawdog the hardware call directly π₯
π CONTEXT π
Called under pf->dplls.lock. so likeβ¦ the lock is held when you call this. Do not come in here uninvited, bestie π
β¨ RETURN β¨
- 0 β success π slay, it worked
- negative β failure π it did not work, and it's telling you so
π SEE ALSO π
okay so this section is huge, and honestly? iconic. The whole ice_dpll cinematic universe lives in the kernel file ./drivers/net/ethernet/intel/ice/ice_dpll.c, plus enum ice_dpll_pin_type(9) and everyone else in the family π
enum ice_dpll_pin_type(9)ice_dpll_is_sw_pin(9)ice_dpll_is_reset(9)ice_dpll_pin_freq_set(9)ice_dpll_frequency_set(9)ice_dpll_input_frequency_set(9)ice_dpll_output_frequency_set(9)ice_dpll_frequency_get(9)ice_dpll_input_frequency_get(9)ice_dpll_output_frequency_get(9)ice_dpll_sw_pin_frequency_set(9)ice_dpll_sw_pin_frequency_get(9)ice_dpll_pin_enable(9)ice_dpll_pin_disable(9)ice_dpll_pin_store_state(9)ice_dpll_rclk_update_e825c(9)ice_dpll_rclk_update(9)ice_dpll_sw_pins_update(9)ice_dpll_pin_state_update(9)ice_dpll_lock_status_get(9)ice_dpll_mode_get(9)ice_dpll_phase_offset_monitor_set(9)ice_dpll_phase_offset_monitor_get(9)ice_dpll_pin_state_set(9)ice_dpll_output_state_set(9)ice_dpll_input_state_set(9)ice_dpll_pin_state_get(9)ice_dpll_output_state_get(9)ice_dpll_input_state_get(9)ice_dpll_sw_pin_notify_peer(9)ice_dpll_sma_direction_set(9)ice_dpll_ufl_pin_state_set(9)ice_dpll_sw_pin_state_get(9)ice_dpll_sma_pin_state_set(9)ice_dpll_input_prio_get(9)ice_dpll_input_prio_set(9)ice_dpll_input_direction(9)ice_dpll_output_direction(9)ice_dpll_pin_sma_direction_set(9)ice_dpll_pin_sw_direction_get(9)ice_dpll_pin_phase_adjust_get(9)ice_dpll_pin_phase_adjust_set(9)ice_dpll_input_phase_adjust_set(9)ice_dpll_output_phase_adjust_set(9)ice_dpll_sw_phase_adjust_get(9)ice_dpll_sw_phase_adjust_set(9)ice_dpll_phase_offset_get(9)ice_dpll_synce_update_e825c(9)ice_dpll_output_esync_set(9)ice_dpll_output_esync_get(9)ice_dpll_input_esync_set(9)ice_dpll_input_esync_get(9)ice_dpll_sw_esync_set(9)ice_dpll_sw_esync_get(9)ice_dpll_input_ref_sync_get(9)ice_dpll_sw_input_ref_sync_get(9)ice_dpll_rclk_state_on_pin_set(9)ice_dpll_rclk_state_on_pin_get(9)ice_dpll_txclk_work(9)ice_dpll_txclk_state_on_dpll_set(9)ice_dpll_txclk_state_on_dpll_get(9)ice_generate_clock_id(9)ice_dpll_pin_ntf(9)ice_dpll_notify_changes(9)ice_dpll_is_pps_phase_monitor(9)ice_dpll_pins_notify_mask(9)ice_dpll_pps_update_phase_offsets(9)ice_dpll_update_state(9)ice_dpll_periodic_work(9)ice_dpll_init_ref_sync_inputs(9)ice_dpll_release_pins(9)ice_dpll_get_pins(9)ice_dpll_unregister_pins(9)ice_dpll_pin_ref_sync_register(9)ice_dpll_register_pins(9)ice_dpll_deinit_direct_pins(9)ice_dpll_init_direct_pins(9)ice_dpll_deinit_rclk_pin(9)ice_dpll_init_pin_common(9)ice_dpll_init_rclk_pin(9)ice_dpll_deinit_pins(9)ice_dpll_init_fwnode_pins(9)ice_dpll_init_pins_e825(9)ice_dpll_init_pins(9)ice_dpll_deinit_dpll(9)ice_dpll_init_dpll(9)ice_dpll_deinit_worker(9)ice_dpll_init_worker(9)ice_dpll_phase_range_set(9)ice_dpll_init_info_pins_generic(9)ice_dpll_init_info_direct_pins(9)ice_dpll_init_info_pin_on_pin_e825c(9)ice_dpll_init_info_rclk_pin(9)ice_dpll_init_info_sw_pins(9)ice_dpll_init_info_txclk_pins_e825c(9)ice_dpll_init_pins_info(9)ice_dpll_deinit_info(9)ice_dpll_init_info_e825c(9)ice_dpll_init_info(9)ice_dpll_deinit(9)ice_dpll_init_e825(9)ice_dpll_init_e810(9)
fr fr, if you're setting a priority without peeking at ice_dpll_input_prio_get(9) and friends first, you're doing main character energy wrong π
that's the whole page, bestie π this lore drop lives in ./drivers/net/ethernet/intel/ice, dated October 2026, and it's the ice_dpll_hw_input_prio_set(9) girl herself β go set some priorities, you've got this πβ¨π¦
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms