ice_dpll_pin_state_set(9)
π
ice_dpll_pin_state_set β Kernel API Manual, but make it cute β¨
okay bestie, welcome to the Kernel API Manual page for ice_dpll_pin_state_set(9) β she's an Intel ice DPLL function and she's here to set a pin state. pull up a chair, we're doing kernel networking today π
β¨ NAME β¨
ice_dpll_pin_state_set β literally her whole job: set the pin's state on dpll. that's it, that's the girl π
πΈ SYNOPSIS πΈ
int ice_dpll_pin_state_set (const struct dpll_pin *pin , void *pin_priv
, const struct dpll_device *dpll , void *dpll_priv , bool enable ,
struct netlink_ext_ack *extack , enum ice_dpll_pin_type pin_type );
like, seven arguments. she's high-maintenance but she delivers π«Ά
π¦ ARGUMENTS π¦
pinβ pointer to a pin. yes, the actual pin. the main character πpin_privβ private data pointer that got passed in when the pin was registered. her little bag of secrets πdpllβ the registered dpll pointer. not a fake dpll, a registered one, ok? πdpll_privβ private data pointer passed on dpll registration. the dpll's own little bag of secrets πenableβ if the pinshalllbe enabled. (three l's, she said what she said π i don't make the rules, i just transcribe them)extackβ error reporting. so when things go sideways, she can tell you how they went sideways πpin_typeβ type of a pin. anenum ice_dpll_pin_type, for the record β¨
π DESCRIPTION π
Set pin state on a pin. that's the description, that's the whole description, no cap. she sets, the pin's state, on the pin. iconic behavior honestly π
π₯ CONTEXT π₯
she acquires pf->dplls.lock while she's doing it. so like, be aware she's holding a lock, bestie β no funny business while she's in there π
β RETURN β
0β OK, or no change required. either way she's happy πΈ- negative β error. she's not happy π
π SEE ALSO π
oh girl, buckle up, this list is long and we are not skipping a single one of them, periodt π§
the kernel file: ./drivers/net/ethernet/intel/ice/ice_dpll.c
enum ice_dpll_pin_type(9)ice_dpll_is_sw_pin(9)ice_dpll_is_reset(9)ice_dpll_pin_freq_set(9)ice_dpll_frequency_set(9)ice_dpll_input_frequency_set(9)ice_dpll_output_frequency_set(9)ice_dpll_frequency_get(9)ice_dpll_input_frequency_get(9)ice_dpll_output_frequency_get(9)ice_dpll_sw_pin_frequency_set(9)ice_dpll_sw_pin_frequency_get(9)ice_dpll_pin_enable(9)ice_dpll_pin_disable(9)ice_dpll_pin_store_state(9)ice_dpll_rclk_update_e825c(9)ice_dpll_rclk_update(9)ice_dpll_sw_pins_update(9)ice_dpll_pin_state_update(9)ice_dpll_hw_input_prio_set(9)ice_dpll_lock_status_get(9)ice_dpll_mode_get(9)ice_dpll_phase_offset_monitor_set(9)ice_dpll_phase_offset_monitor_get(9)ice_dpll_output_state_set(9)ice_dpll_input_state_set(9)ice_dpll_pin_state_get(9)ice_dpll_output_state_get(9)ice_dpll_input_state_get(9)ice_dpll_sw_pin_notify_peer(9)ice_dpll_sma_direction_set(9)ice_dpll_ufl_pin_state_set(9)ice_dpll_sw_pin_state_get(9)ice_dpll_sma_pin_state_set(9)ice_dpll_input_prio_get(9)ice_dpll_input_prio_set(9)ice_dpll_input_direction(9)ice_dpll_output_direction(9)ice_dpll_pin_sma_direction_set(9)ice_dpll_pin_sw_direction_get(9)ice_dpll_pin_phase_adjust_get(9)ice_dpll_pin_phase_adjust_set(9)ice_dpll_input_phase_adjust_set(9)ice_dpll_output_phase_adjust_set(9)ice_dpll_sw_phase_adjust_get(9)ice_dpll_sw_phase_adjust_set(9)ice_dpll_phase_offset_get(9)ice_dpll_synce_update_e825c(9)ice_dpll_output_esync_set(9)ice_dpll_output_esync_get(9)ice_dpll_input_esync_set(9)ice_dpll_input_esync_get(9)ice_dpll_sw_esync_set(9)ice_dpll_sw_esync_get(9)ice_dpll_input_ref_sync_get(9)ice_dpll_sw_input_ref_sync_get(9)ice_dpll_rclk_state_on_pin_set(9)ice_dpll_rclk_state_on_pin_get(9)ice_dpll_txclk_work(9)ice_dpll_txclk_state_on_dpll_set(9)ice_dpll_txclk_state_on_dpll_get(9)ice_generate_clock_id(9)ice_dpll_pin_ntf(9)ice_dpll_notify_changes(9)ice_dpll_is_pps_phase_monitor(9)ice_dpll_pins_notify_mask(9)ice_dpll_pps_update_phase_offsets(9)ice_dpll_update_state(9)ice_dpll_periodic_work(9)ice_dpll_init_ref_sync_inputs(9)ice_dpll_release_pins(9)ice_dpll_get_pins(9)ice_dpll_unregister_pins(9)ice_dpll_pin_ref_sync_register(9)ice_dpll_register_pins(9)ice_dpll_deinit_direct_pins(9)ice_dpll_init_direct_pins(9)ice_dpll_deinit_rclk_pin(9)ice_dpll_init_pin_common(9)ice_dpll_init_rclk_pin(9)ice_dpll_deinit_pins(9)ice_dpll_init_fwnode_pins(9)ice_dpll_init_pins_e825(9)ice_dpll_init_pins(9)ice_dpll_deinit_dpll(9)ice_dpll_init_dpll(9)ice_dpll_deinit_worker(9)ice_dpll_init_worker(9)ice_dpll_phase_range_set(9)ice_dpll_init_info_pins_generic(9)ice_dpll_init_info_direct_pins(9)ice_dpll_init_info_pin_on_pin_e825c(9)ice_dpll_init_info_rclk_pin(9)ice_dpll_init_info_sw_pins(9)ice_dpll_init_info_txclk_pins_e825c(9)ice_dpll_init_pins_info(9)ice_dpll_deinit_info(9)ice_dpll_init_info_e825c(9)ice_dpll_init_info(9)ice_dpll_deinit(9)ice_dpll_init_e825(9)ice_dpll_init_e810(9)
see? ate. every single one. no skipping, no summarizing, we respect the list π
okay that's the whole page bestie!! source and version vibes: this one lives in ./drivers/net/ethernet/intel/ice, dated October 2026, and the manual is ice_dpll_pin_state_set(9) in the Kernel API Manual β go forth and set some pin states, you're gonna slay ππ«Άπ
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms