ice_dpll_mode_get(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… ice_dpll_mode_get(9) β€” from the Kernel API Manual, bestie ✨

Okay so picture this: you're deep in the ice driver, the DPLL subsystem is doing its whole clock-sync main-character thing, and somebody needs to know what mode this dpll is vibing in. That's this function. It's a callback, it's registered with the dpll subsystem, and it hands back the working mode. Slay.


🌸 NAME 🌸

ice_dpll_mode_get β€” get dpll's working mode. That's it. That's the whole gig. πŸŽ€


✨ SYNOPSIS ✨

int ice_dpll_mode_get (const struct dpll_device *dpll , void *dpll_priv
, enum dpll_mode *mode , struct netlink_ext_ack *extack );

Like, look at her. Four params, one int return, zero notes. Iconic.


πŸ¦‹ ARGUMENTS πŸ¦‹

  • dpll β€” the registered dpll pointer. This is the dpll, the one that got registered. Not a lookalike, not a cousin. 🫢
  • dpll_priv β€” the private data pointer that was passed on dpll registration. So if you handed it over at registration time, it comes right back to you here. Full circle moment.
  • mode β€” on success this holds the current working mode of the dpll. So yeah, it's an out-param. It's giving "I'll tell you, but only if things went well." πŸ’–
  • extack β€” error reporting. The netlink extended ACK, doing its little messenger thing when stuff goes sideways.

πŸ’œ DESCRIPTION πŸ’œ

Dpll subsystem callback. Provides working mode of dpll.

No cap, that's the whole description β€” it's a callback in the dpll subsystem, and its job is literally to provide the working mode of the dpll. Lowkey the most straightforward function in this entire file. πŸ’…


πŸ”₯ CONTEXT πŸ”₯

Acquires pf->dplls.lock

Heads up bestie: this thing takes that lock. So don't go calling it from somewhere that's already holding it and then act surprised. 😭

πŸ‘‘ RETURN πŸ‘‘

  • 0 β€” success. We ate. 🌈
  • negative β€” failure. It's giving "not today." πŸ’€

🧚 SEE ALSO 🧚

First up, the source file, because you will want to go read it:

./drivers/net/ethernet/intel/ice/ice_dpll.c, plus enum ice_dpll_pin_type(9).

And now the whole extended family β€” because apparently everyone in ice_dpll.c got an invite to this party and we are NOT leaving anyone out:

ice_dpll_is_sw_pin(9), ice_dpll_is_reset(9), ice_dpll_pin_freq_set(9), ice_dpll_frequency_set(9), ice_dpll_input_frequency_set(9), ice_dpll_output_frequency_set(9), ice_dpll_frequency_get(9), ice_dpll_input_frequency_get(9), ice_dpll_output_frequency_get(9), ice_dpll_sw_pin_frequency_set(9), ice_dpll_sw_pin_frequency_get(9), ice_dpll_pin_enable(9), ice_dpll_pin_disable(9), ice_dpll_pin_store_state(9), ice_dpll_rclk_update_e825c(9), ice_dpll_rclk_update(9), ice_dpll_sw_pins_update(9), ice_dpll_pin_state_update(9), ice_dpll_hw_input_prio_set(9), ice_dpll_lock_status_get(9), ice_dpll_phase_offset_monitor_set(9), ice_dpll_phase_offset_monitor_get(9), ice_dpll_pin_state_set(9), ice_dpll_output_state_set(9), ice_dpll_input_state_set(9), ice_dpll_pin_state_get(9), ice_dpll_output_state_get(9), ice_dpll_input_state_get(9).

Still going, bestie, don't scroll away yet 🫢:

ice_dpll_sw_pin_notify_peer(9), ice_dpll_sma_direction_set(9), ice_dpll_ufl_pin_state_set(9), ice_dpll_sw_pin_state_get(9), ice_dpll_sma_pin_state_set(9), ice_dpll_input_prio_get(9), ice_dpll_input_prio_set(9), ice_dpll_input_direction(9), ice_dpll_output_direction(9), ice_dpll_pin_sma_direction_set(9), ice_dpll_pin_sw_direction_get(9), ice_dpll_pin_phase_adjust_get(9), ice_dpll_pin_phase_adjust_set(9), ice_dpll_input_phase_adjust_set(9), ice_dpll_output_phase_adjust_set(9), ice_dpll_sw_phase_adjust_get(9), ice_dpll_sw_phase_adjust_set(9), ice_dpll_phase_offset_get(9), ice_dpll_synce_update_e825c(9), ice_dpll_output_esync_set(9), ice_dpll_output_esync_get(9), ice_dpll_input_esync_set(9), ice_dpll_input_esync_get(9), ice_dpll_sw_esync_set(9), ice_dpll_sw_esync_get(9), ice_dpll_input_ref_sync_get(9), ice_dpll_sw_input_ref_sync_get(9), ice_dpll_rclk_state_on_pin_set(9), ice_dpll_rclk_state_on_pin_get(9), ice_dpll_txclk_work(9), ice_dpll_txclk_state_on_dpll_set(9), ice_dpll_txclk_state_on_dpll_get(9), ice_generate_clock_id(9), ice_dpll_pin_ntf(9), ice_dpll_notify_changes(9), ice_dpll_is_pps_phase_monitor(9), ice_dpll_pins_notify_mask(9), ice_dpll_pps_update_phase_offsets(9), ice_dpll_update_state(9), ice_dpll_periodic_work(9), ice_dpll_init_ref_sync_inputs(9).

Almost there, I promise πŸ’–:

ice_dpll_release_pins(9), ice_dpll_get_pins(9), ice_dpll_unregister_pins(9), ice_dpll_pin_ref_sync_register(9), ice_dpll_register_pins(9), ice_dpll_deinit_direct_pins(9), ice_dpll_init_direct_pins(9), ice_dpll_deinit_rclk_pin(9), ice_dpll_init_pin_common(9), ice_dpll_init_rclk_pin(9), ice_dpll_deinit_pins(9), ice_dpll_init_fwnode_pins(9), ice_dpll_init_pins_e825(9), ice_dpll_init_pins(9), ice_dpll_deinit_dpll(9), ice_dpll_init_dpll(9), ice_dpll_deinit_worker(9), ice_dpll_init_worker(9), ice_dpll_phase_range_set(9), ice_dpll_init_info_pins_generic(9), ice_dpll_init_info_direct_pins(9), ice_dpll_init_info_pin_on_pin_e825c(9), ice_dpll_init_info_rclk_pin(9), ice_dpll_init_info_sw_pins(9), ice_dpll_init_info_txclk_pins_e825c(9), ice_dpll_init_pins_info(9).

And the init/deinit finale πŸŽ€:

ice_dpll_deinit_info(9), ice_dpll_init_info_e825c(9), ice_dpll_init_info(9), ice_dpll_deinit(9), ice_dpll_init_e825(9), ice_dpll_init_e810(9).


Okay that's the whole page, no skips, no cuts, iykyk. This little beauty lives in ./drivers/net/ethernet/intel/ice, dated October 2026, and the page itself is ice_dpll_mode_get(9) β€” go get that mode bestie, you've got this πŸ’…βœ¨

πŸ“¦ where this page comes from