ice_dpll_pin_freq_set(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– ice_dpll_pin_freq_set β€” setting a pin's frequency, bestie edition πŸ’–

Okay so this one's from the Kernel API Manual (section 9, kernel internals, iykyk) and it's literally the function that sets the frequency on a pin. That's it. That's the vibe. ✨


🌸 NAME 🌸

ice_dpll_pin_freq_set β€” set pin's frequency 🎯


πŸŽ€ SYNOPSIS πŸŽ€

int ice_dpll_pin_freq_set (struct ice_pf *pf , struct ice_dpll_pin *pin
, enum ice_dpll_pin_type pin_type , const u32 freq , struct
netlink_ext_ack *extack );

πŸ¦‹ ARGUMENTS πŸ¦‹

  • pf β€” the private board structure. your main character struct, honestly 🫢
  • pin β€” pointer to a pin πŸ“Œ
  • pin_type β€” type of pin being configured (yes they make you say it out loud, no cap)
  • freq β€” the frequency to be set 🎚️
  • extack β€” error reporting, aka the friend who tells you when something went wrong 😭

✨ DESCRIPTION ✨

Set the requested frequency on a pin. That's the whole assignment, and it ate. πŸ’…πŸ”₯


πŸ’œ CONTEXT πŸ’œ

Called under pf->dplls.lock β€” locked and loaded, bestie. πŸ”’βœ¨


πŸ‘‘ RETURN πŸ‘‘

  • 0 β€” success, slay πŸŽ‰
  • negative β€” error on AQ or wrong pin type given πŸ’€ (so like, check your pin type first, fr fr)

🌈 SEE ALSO 🌈

Kernel file ./drivers/net/ethernet/intel/ice/ice_dpll.c, plus this whole friend group:

enum ice_dpll_pin_type(9), ice_dpll_is_sw_pin(9), ice_dpll_is_reset(9), ice_dpll_frequency_set(9), ice_dpll_input_frequency_set(9), ice_dpll_output_frequency_set(9), ice_dpll_frequency_get(9), ice_dpll_input_frequency_get(9), ice_dpll_output_frequency_get(9), ice_dpll_sw_pin_frequency_set(9), ice_dpll_sw_pin_frequency_get(9), ice_dpll_pin_enable(9), ice_dpll_pin_disable(9), ice_dpll_pin_store_state(9), ice_dpll_rclk_update_e825c(9), ice_dpll_rclk_update(9), ice_dpll_sw_pins_update(9), ice_dpll_pin_state_update(9), ice_dpll_hw_input_prio_set(9), ice_dpll_lock_status_get(9), ice_dpll_mode_get(9), ice_dpll_phase_offset_monitor_set(9), ice_dpll_phase_offset_monitor_get(9), ice_dpll_pin_state_set(9), ice_dpll_output_state_set(9), ice_dpll_input_state_set(9), ice_dpll_pin_state_get(9), ice_dpll_output_state_get(9), ice_dpll_input_state_get(9), ice_dpll_sw_pin_notify_peer(9), ice_dpll_sma_direction_set(9), ice_dpll_ufl_pin_state_set(9), ice_dpll_sw_pin_state_get(9), ice_dpll_sma_pin_state_set(9), ice_dpll_input_prio_get(9), ice_dpll_input_prio_set(9), ice_dpll_input_direction(9), ice_dpll_output_direction(9), ice_dpll_pin_sma_direction_set(9), ice_dpll_pin_sw_direction_get(9), ice_dpll_pin_phase_adjust_get(9), ice_dpll_pin_phase_adjust_set(9), ice_dpll_input_phase_adjust_set(9), ice_dpll_output_phase_adjust_set(9), ice_dpll_sw_phase_adjust_get(9), ice_dpll_sw_phase_adjust_set(9), ice_dpll_phase_offset_get(9), ice_dpll_synce_update_e825c(9), ice_dpll_output_esync_set(9), ice_dpll_output_esync_get(9), ice_dpll_input_esync_set(9), ice_dpll_input_esync_get(9), ice_dpll_sw_esync_set(9), ice_dpll_sw_esync_get(9), ice_dpll_input_ref_sync_get(9), ice_dpll_sw_input_ref_sync_get(9), ice_dpll_rclk_state_on_pin_set(9), ice_dpll_rclk_state_on_pin_get(9), ice_dpll_txclk_work(9), ice_dpll_txclk_state_on_dpll_set(9), ice_dpll_txclk_state_on_dpll_get(9), ice_generate_clock_id(9), ice_dpll_pin_ntf(9), ice_dpll_notify_changes(9), ice_dpll_is_pps_phase_monitor(9), ice_dpll_pins_notify_mask(9), ice_dpll_pps_update_phase_offsets(9), ice_dpll_update_state(9), ice_dpll_periodic_work(9), ice_dpll_init_ref_sync_inputs(9), ice_dpll_release_pins(9), ice_dpll_get_pins(9), ice_dpll_unregister_pins(9), ice_dpll_pin_ref_sync_register(9), ice_dpll_register_pins(9), ice_dpll_deinit_direct_pins(9), ice_dpll_init_direct_pins(9), ice_dpll_deinit_rclk_pin(9), ice_dpll_init_pin_common(9), ice_dpll_init_rclk_pin(9), ice_dpll_deinit_pins(9), ice_dpll_init_fwnode_pins(9), ice_dpll_init_pins_e825(9), ice_dpll_init_pins(9), ice_dpll_deinit_dpll(9), ice_dpll_init_dpll(9), ice_dpll_deinit_worker(9), ice_dpll_init_worker(9), ice_dpll_phase_range_set(9), ice_dpll_init_info_pins_generic(9), ice_dpll_init_info_direct_pins(9), ice_dpll_init_info_pin_on_pin_e825c(9), ice_dpll_init_info_rclk_pin(9), ice_dpll_init_info_sw_pins(9), ice_dpll_init_info_txclk_pins_e825c(9), ice_dpll_init_pins_info(9), ice_dpll_deinit_info(9), ice_dpll_init_info_e825c(9), ice_dpll_init_info(9), ice_dpll_deinit(9), ice_dpll_init_e825(9), ice_dpll_init_e810(9)


And that's the whole thing, bestie β€” brought to you by the ./drivers/net/ethernet/intel/ice source, dated October 2026. Go forth and set those frequencies. πŸ’…πŸŽ€πŸ¦‹πŸŒΈβœ¨πŸ’–

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