ice_dpll_init_dpll(9)

💅 ice_dpll_init_dpll — a Kernel API Manual moment (yes, that Kernel API Manual, section 9, we're fancy)

okay so bestie, gather round, because we're about to initialize a DPLL device in the dpll subsystem and honestly? it's giving main character energy 🎀 this whole page lives in section 9 of the kernel API manual and it's a whole vibe.

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✨ NAME ✨

ice_dpll_init_dpll — initialize dpll device in dpll subsystem 🌸

like, the entire job. spin up the dpll. that's it. that's the function.

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✨ SYNOPSIS ✨

int ice_dpll_init_dpll (struct ice_pf *pf , struct ice_dpll *d , bool
cgu , enum dpll_type type );

she takes four things and returns an int, no notes 💅

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✨ ARGUMENTS ✨

• pf — the board private structure 🫶 this is the NIC's whole personality/locker, basically.
• d — the dpll to be initialized ✨ the little guy we're waking up.
• cgu — bool; true if cgu is present and controlled by this NIC 👑 this flag matters, keep reading.
• type — type of dpll being initialized 🦋 an enum dpll_type, so she comes in a few flavors.

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✨ DESCRIPTION ✨

okay so here's the tea 🍓 this function allocates a DPLL instance for this board inside the dpll subsystem — like, it gets the dpll its own little seat at the table.

and if cgu is controlled by this NIC, it also registers the DPLL with the callback ops 🔥 not me handing out callbacks like friendship bracelets. that cgu condition is the whole plot twist, don't skip it bestie.

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✨ RETURN ✨

• 0 — success 🎉 slay, we ate, everything is iconic.
• negative — initialization failure reason 😭 it literally tells you why it went wrong, which is more than some people do.

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✨ SEE ALSO ✨

first up, the source file itself, because iykyk:

Kernel file ./drivers/net/ethernet/intel/ice/ice_dpll.c

and then... the extended universe 🌈 (yes, every single one, i promised):

enum ice_dpll_pin_type(9), ice_dpll_is_sw_pin(9), ice_dpll_is_reset(9), ice_dpll_pin_freq_set(9), ice_dpll_frequency_set(9), ice_dpll_input_frequency_set(9), ice_dpll_output_frequency_set(9), ice_dpll_frequency_get(9), ice_dpll_input_frequency_get(9), ice_dpll_output_frequency_get(9), ice_dpll_sw_pin_frequency_set(9), ice_dpll_sw_pin_frequency_get(9), ice_dpll_pin_enable(9), ice_dpll_pin_disable(9), ice_dpll_pin_store_state(9), ice_dpll_rclk_update_e825c(9), ice_dpll_rclk_update(9), ice_dpll_sw_pins_update(9), ice_dpll_pin_state_update(9), ice_dpll_hw_input_prio_set(9), ice_dpll_lock_status_get(9), ice_dpll_mode_get(9), ice_dpll_phase_offset_monitor_set(9), ice_dpll_phase_offset_monitor_get(9), ice_dpll_pin_state_set(9), ice_dpll_output_state_set(9), ice_dpll_input_state_set(9), ice_dpll_pin_state_get(9), ice_dpll_output_state_get(9), ice_dpll_input_state_get(9), ice_dpll_sw_pin_notify_peer(9), ice_dpll_sma_direction_set(9), ice_dpll_ufl_pin_state_set(9), ice_dpll_sw_pin_state_get(9), ice_dpll_sma_pin_state_set(9), ice_dpll_input_prio_get(9), ice_dpll_input_prio_set(9), ice_dpll_input_direction(9), ice_dpll_output_direction(9), ice_dpll_pin_sma_direction_set(9), ice_dpll_pin_sw_direction_get(9), ice_dpll_pin_phase_adjust_get(9), ice_dpll_pin_phase_adjust_set(9), ice_dpll_input_phase_adjust_set(9), ice_dpll_output_phase_adjust_set(9), ice_dpll_sw_phase_adjust_get(9), ice_dpll_sw_phase_adjust_set(9), ice_dpll_phase_offset_get(9), ice_dpll_synce_update_e825c(9), ice_dpll_output_esync_set(9), ice_dpll_output_esync_get(9), ice_dpll_input_esync_set(9), ice_dpll_input_esync_get(9), ice_dpll_sw_esync_set(9), ice_dpll_sw_esync_get(9), ice_dpll_input_ref_sync_get(9), ice_dpll_sw_input_ref_sync_get(9), ice_dpll_rclk_state_on_pin_set(9), ice_dpll_rclk_state_on_pin_get(9), ice_dpll_txclk_work(9), ice_dpll_txclk_state_on_dpll_set(9), ice_dpll_txclk_state_on_dpll_get(9), ice_generate_clock_id(9), ice_dpll_pin_ntf(9), ice_dpll_notify_changes(9), ice_dpll_is_pps_phase_monitor(9), ice_dpll_pins_notify_mask(9), ice_dpll_pps_update_phase_offsets(9), ice_dpll_update_state(9), ice_dpll_periodic_work(9), ice_dpll_init_ref_sync_inputs(9), ice_dpll_release_pins(9), ice_dpll_get_pins(9), ice_dpll_unregister_pins(9), ice_dpll_pin_ref_sync_register(9), ice_dpll_register_pins(9), ice_dpll_deinit_direct_pins(9), ice_dpll_init_direct_pins(9), ice_dpll_deinit_rclk_pin(9), ice_dpll_init_pin_common(9), ice_dpll_init_rclk_pin(9), ice_dpll_deinit_pins(9), ice_dpll_init_fwnode_pins(9), ice_dpll_init_pins_e825(9), ice_dpll_init_pins(9), ice_dpll_deinit_dpll(9), ice_dpll_deinit_worker(9), ice_dpll_init_worker(9), ice_dpll_phase_range_set(9), ice_dpll_init_info_pins_generic(9), ice_dpll_init_info_direct_pins(9), ice_dpll_init_info_pin_on_pin_e825c(9), ice_dpll_init_info_rclk_pin(9), ice_dpll_init_info_sw_pins(9), ice_dpll_init_info_txclk_pins_e825c(9), ice_dpll_init_pins_info(9), ice_dpll_deinit_info(9), ice_dpll_init_info_e825c(9), ice_dpll_init_info(9), ice_dpll_deinit(9), ice_dpll_init_e825(9), ice_dpll_init_e810(9)

like, that's the whole group chat 😭 every single one of them.

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ok real talk bestie 💀 this one is the init function — everything else in that list is downstream of whether you got pf, d, cgu and type right. no cap.

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that's the page! 🎀 brought to you by the fine folks over at ./drivers/net/ethernet/intel/ice, dated October 2026 — periodt, go init something 💜🌸