ice_dpll_txc..._on_dpll_set(9)

📦 version 7.3.1, in nixpkgs unstable

💅 NAME

ice_dpll_txclk_state_on_dpll_set — bestie, this one sets a state on the TX clk pin ✨

🎀 SYNOPSIS

int ice_dpll_txclk_state_on_dpll_set (const struct dpll_pin *pin , void
*pin_priv , const struct dpll_device *dpll , void *dpll_priv , enum
dpll_pin_state state , struct netlink_ext_ack *extack );

🌸 ARGUMENTS

Okay so here's who's showing up to this function call, no gatekeeping:

  • pin — pointer to a pin 💅 that's literally it, it's the pin
  • pin_priv — the private data pointer you passed on pin registration (iykyk, it's the little secret bag of data that came with the pin)
  • dpll — the registered dpll pointer, the main character 👑
  • dpll_priv — private data pointer you passed on dpll registration, the dpll's own little secret bag
  • state — the state to be set on the pin, aka the whole reason we're here
  • extack — error reporting, so when stuff goes sideways you actually find out 😭

🦋 DESCRIPTION

It's a Dpll subsystem callback, and what it does is set a state of a Tx reference clock pin 🎀 lowkey iconic behavior, and ngl it's exactly what it says on the tin: Tx clk pin, state, set. Periodt.

🔥 CONTEXT

Acquires and releases pf->dplls.lock. So yeah, she grabs the lock and lets it go — don't be weird about it 🙈

Heads up bestie: the function takes that lock, so don't go calling it from somewhere that's already holding pf->dplls.lock and expect a good time 💀

⭐ RETURN

  • 0 — success 🎉 slay
  • negative — failure 😭 it's giving error

💜 SEE ALSO

Kernel file ./drivers/net/ethernet/intel/ice/ice_dpll.c and honestly the whole friend group: enum ice_dpll_pin_type(9), ice_dpll_is_sw_pin(9), ice_dpll_is_reset(9), ice_dpll_pin_freq_set(9), ice_dpll_frequency_set(9), ice_dpll_input_frequency_set(9), ice_dpll_output_frequency_set(9), ice_dpll_frequency_get(9), ice_dpll_input_frequency_get(9), ice_dpll_output_frequency_get(9), ice_dpll_sw_pin_frequency_set(9), ice_dpll_sw_pin_frequency_get(9), ice_dpll_pin_enable(9), ice_dpll_pin_disable(9), ice_dpll_pin_store_state(9), ice_dpll_rclk_update_e825c(9), ice_dpll_rclk_update(9), ice_dpll_sw_pins_update(9), ice_dpll_pin_state_update(9), ice_dpll_hw_input_prio_set(9), ice_dpll_lock_status_get(9), ice_dpll_mode_get(9), ice_dpll_phase_offset_monitor_set(9), ice_dpll_phase_offset_monitor_get(9), ice_dpll_pin_state_set(9), ice_dpll_output_state_set(9), ice_dpll_input_state_set(9), ice_dpll_pin_state_get(9), ice_dpll_output_state_get(9), ice_dpll_input_state_get(9), ice_dpll_sw_pin_notify_peer(9), ice_dpll_sma_direction_set(9), ice_dpll_ufl_pin_state_set(9), ice_dpll_sw_pin_state_get(9), ice_dpll_sma_pin_state_set(9), ice_dpll_input_prio_get(9), ice_dpll_input_prio_set(9), ice_dpll_input_direction(9), ice_dpll_output_direction(9), ice_dpll_pin_sma_direction_set(9), ice_dpll_pin_sw_direction_get(9), ice_dpll_pin_phase_adjust_get(9), ice_dpll_pin_phase_adjust_set(9), ice_dpll_input_phase_adjust_set(9), ice_dpll_output_phase_adjust_set(9), ice_dpll_sw_phase_adjust_get(9), ice_dpll_sw_phase_adjust_set(9), ice_dpll_phase_offset_get(9), ice_dpll_synce_update_e825c(9), ice_dpll_output_esync_set(9), ice_dpll_output_esync_get(9), ice_dpll_input_esync_set(9), ice_dpll_input_esync_get(9), ice_dpll_sw_esync_set(9), ice_dpll_sw_esync_get(9), ice_dpll_input_ref_sync_get(9), ice_dpll_sw_input_ref_sync_get(9), ice_dpll_rclk_state_on_pin_set(9), ice_dpll_rclk_state_on_pin_get(9), ice_dpll_txclk_work(9), ice_dpll_txclk_state_on_dpll_get(9), ice_generate_clock_id(9), ice_dpll_pin_ntf(9), ice_dpll_notify_changes(9), ice_dpll_is_pps_phase_monitor(9), ice_dpll_pins_notify_mask(9), ice_dpll_pps_update_phase_offsets(9), ice_dpll_update_state(9), ice_dpll_periodic_work(9), ice_dpll_init_ref_sync_inputs(9), ice_dpll_release_pins(9), ice_dpll_get_pins(9), ice_dpll_unregister_pins(9), ice_dpll_pin_ref_sync_register(9), ice_dpll_register_pins(9), ice_dpll_deinit_direct_pins(9), ice_dpll_init_direct_pins(9), ice_dpll_deinit_rclk_pin(9), ice_dpll_init_pin_common(9), ice_dpll_init_rclk_pin(9), ice_dpll_deinit_pins(9), ice_dpll_init_fwnode_pins(9), ice_dpll_init_pins_e825(9), ice_dpll_init_pins(9), ice_dpll_deinit_dpll(9), ice_dpll_init_dpll(9), ice_dpll_deinit_worker(9), ice_dpll_init_worker(9), ice_dpll_phase_range_set(9), ice_dpll_init_info_pins_generic(9), ice_dpll_init_info_direct_pins(9), ice_dpll_init_info_pin_on_pin_e825c(9), ice_dpll_init_info_rclk_pin(9), ice_dpll_init_info_sw_pins(9), ice_dpll_init_info_txclk_pins_e825c(9), ice_dpll_init_pins_info(9), ice_dpll_deinit_info(9), ice_dpll_init_info_e825c(9), ice_dpll_init_info(9), ice_dpll_deinit(9), ice_dpll_init_e825(9), ice_dpll_init_e810(9) 💖

okay that's the whole page bestie, ily, go set some states ✨

This one lives over in ./drivers/net/ethernet/intel/ice and it's dated October 2026 — so like, future vibes, but the kernel manual said it, not me 🫶💅

📦 where this page comes from