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S (continued)

struct dprc_region_desc(9)Mappable region descriptor✨
struct dpseci_attr(9)Structure representing DPSECI attributes✨
struct dpseci_cfg(9)Structure representing DPSECI configuration✨
struct dpseci_congestion_notification_cfg(9)congestion notification configuration✨
struct dpseci_dest_cfg(9)Structure representing DPSECI destination parameters✨
struct dpseci_rx_queue_attr(9)Structure representing attributes of Rx queues✨
struct dpseci_rx_queue_cfg(9)DPSECI RX queue configuration✨
struct dpseci_sec_attr(9)Structure representing attributes of the SEC hardware accelerator✨
struct dpseci_tx_queue_attr(9)Structure representing attributes of Tx queues✨
struct dpsw_acl_cfg(9)ACL Configuration✨
struct dpsw_acl_entry_cfg(9)ACL entry✨
struct dpsw_acl_fields(9)ACL fields.✨
struct dpsw_acl_if_cfg(9)List of interfaces to associate with an ACL table✨
struct dpsw_acl_key(9)ACL key✨
struct dpsw_acl_result(9)ACL action✨
struct dpsw_attr(9)Structure representing DPSW attributes✨
struct dpsw_ctrl_if_attr(9)Control interface attributes✨
struct dpsw_ctrl_if_pools_cfg(9)Control interface buffer pools configuration✨
struct dpsw_fdb_attr(9)FDB Attributes✨
struct dpsw_fdb_cfg(9)FDB Configuration✨
struct dpsw_fdb_multicast_cfg(9)Multi-cast entry configuration✨
struct dpsw_fdb_unicast_cfg(9)Unicast entry configuration✨
struct dpsw_if_attr(9)Structure representing DPSW interface attributes✨
struct dpsw_irq_cfg(9)IRQ configuration✨
struct dpsw_lag_cfg(9)Configuration structure for a LAG group✨
struct dpsw_link_cfg(9)Structure representing DPSW link configuration✨
struct dpsw_link_state(9)Structure representing DPSW link state✨
struct dpsw_reflection_cfg(9)Structure representing the mirroring config✨
struct dpsw_stp_cfg(9)Spanning Tree Protocol (STP) Configuration✨
struct dpsw_tci_cfg(9)Tag Control Information (TCI) configuration✨
struct dpsw_vlan_cfg(9)VLAN Configuration✨
struct dpsw_vlan_if_cfg(9)Set of VLAN Interfaces✨
struct dpu_caps(9)define DPU capabilities @max_mixer_width max layer mixer line width support. @max_mixer_blendstages max layer mixer blend stages or supported z order @has_src_split source split feature status…✨
struct dpu_cdm_cfg(9)information of chroma down blocks @name string name for debug purposes @id enum identifying this block @base register offset of this block✨
struct dpu_core_perf(9)definition of core performance context✨
struct dpu_core_perf_params(9)definition of performance parameters✨
struct dpu_core_perf_tune(9)definition of performance tuning control✨
struct dpu_crtc(9)virtualized CRTC data structure✨
struct dpu_crtc_frame_event(9)stores crtc frame event for crtc processing✨
struct dpu_crtc_mixer(9)stores the map for each virtual pipeline in the CRTC✨
struct dpu_crtc_smmu_state_data(9)stores the smmu state and transition type✨
struct dpu_crtc_state(9)dpu container for atomic crtc state✨
struct dpu_danger_safe_status(9)danger and safe status signals✨
struct dpu_drm_de_v1(9)version 1 of detail enhancer structure✨
struct dpu_drm_pix_ext_v1(9)version 1 of pixel ext structure✨
struct dpu_drm_scaler_v2(9)version 2 of struct dpu_drm_scaler✨
struct dpu_dsc_blk(9)DSC Encoder sub-blk information✨
struct dpu_dsc_cfg(9)information of DSC blocks @id enum identifying this block @base register offset of this block✨
struct dpu_dsc_sub_blks(9)DSC sub-blks✨
struct dpu_dspp_cfg(9)information of DSPP blocks @id enum identifying this block @base register offset of this block supported by this block @sblk sub-blocks information✨
struct dpu_dspp_sub_blks(9)Information of DSPP block✨
struct dpu_enc_phys_init_params(9)initialization parameters for phys encs✨
struct dpu_encoder_phys(9)physical encoder that drives a single INTF block tied to a specific panel / sub-panel. Abstract type, sub-classed by phys_vid or phys_cmd for video mode or command mode encs respectively.✨
struct dpu_encoder_phys_cmd(9)sub-class of dpu_encoder_phys to handle command mode specific operations✨
struct dpu_encoder_phys_ops(9)Interface the physical encoders provide to the containing virtual encoder.✨
struct dpu_encoder_phys_wb(9)sub-class of dpu_encoder_phys to handle command mode specific operations✨
struct dpu_encoder_virt(9)virtual encoder. Container of one or more physical encoders. Virtual encoder manages one "logical" display. Physical encoders manage one intf block, tied to a specific panel/sub- panel. Virtual…✨
struct dpu_hw_blk(9)opaque hardware block object✨
struct dpu_hw_cdm(9)cdm description✨
struct dpu_hw_cdm_cfg(9)current configuration of CDM block✨
struct dpu_hw_cdm_ops(9)Interface to the chroma down Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_ctl(9)CTL PATH driver object✨
struct dpu_hw_ctl_ops(9)Interface to the wb Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_cwb(9)CWB mux driver object✨
struct dpu_hw_cwb_ops(9)Interface to the cwb hw driver functions✨
struct dpu_hw_cwb_setup_cfg(9)Describes configuration for CWB mux✨
struct dpu_hw_dither_cfg(9)dither feature structure✨
struct dpu_hw_dsc_ops(9)interface to the dsc hardware driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_dspp(9)dspp description✨
struct dpu_hw_dspp_ops(9)interface to the dspp hardware driver functions Caller must call the init function to get the dspp context for each dspp Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_fmt_layout(9)format information of the source pixel data✨
struct dpu_hw_gc_lut(9)gc lut feature structure✨
struct dpu_hw_intf_cfg(9)Describes how the DPU writes data to output interface✨
struct dpu_hw_intf_ops(9)Interface to the interface Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_intr(9)hw interrupts handling data structure✨
struct dpu_hw_lm_ops(9)Interface to the mixer Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_mdp_ops(9)interface to the MDP TOP Hw driver functions Assumption is these functions will be called after clocks are enabled.✨
struct dpu_hw_merge_3d_ops(9)Interface to the merge_3d Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_pcc_cfg(9)pcc feature structure✨
struct dpu_hw_pcc_coeff(9)PCC coefficient structure for each color component.✨
struct dpu_hw_pingpong_ops(9)Interface to the pingpong Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_pipe_ts_cfg(9)traffic shaper configuration✨
struct dpu_hw_pp_vsync_info(9)Struct contains parameters to configure read and write pointers for command mode panels✨
struct dpu_hw_qos_cfg(9)pipe QoS configuration✨
struct dpu_hw_scaler3_cfg(9)QSEEDv3 configuration✨
struct dpu_hw_scaler3_de_cfg(9)QSEEDv3 detail enhancer configuration✨
struct dpu_hw_sspp(9)pipe description✨
struct dpu_hw_sspp_ops(9)interface to the SSPP Hw driver functions Caller must call the init function to get the pipe context for each pipe Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_stage_cfg(9)blending stage cfg✨
struct dpu_hw_tear_check(9)Struct contains parameters to configure tear- effect module. This structure is used to configure tear-check logic present either in ping-pong or in interface module.✨
struct dpu_hw_vbif_ops(9)Interface to the VBIF hardware driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_wb(9)WB driver object✨
struct dpu_hw_wb_ops(9)Interface to the wb hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_intf_cfg(9)information of timing engine blocks @id enum identifying this block @base register offset of this block✨
struct dpu_intr_reg(9)array of DPU register sets✨
struct dpu_lm_cfg(9)information of layer mixer blocks✨
struct dpu_lm_sub_blks(9)information of mixer block✨
struct dpu_mdss_cfg(9)information of MDSS HW This is the main catalog data structure representing this HW version. Contains dpu's major and minor versions, number of instances, register offsets, capabilities of the all…✨
struct dpu_mdss_color(9)mdss color description color 0 : green color 1 : blue color 2 : red color 3 : alpha✨
struct dpu_mdss_version(9)DPU's major and minor versions✨
struct dpu_merge_3d_cfg(9)information of DSPP blocks @id enum identifying this block @base register offset of this block @sblk sub- blocks information✨
struct dpu_perf_cdp_cfg(9)define CDP use case configuration✨
struct dpu_perf_cfg(9)performance control settings @max_bw_low low threshold of maximum bandwidth (kbps) @max_bw_high high threshold of maximum bandwidth (kbps) @min_core_ib minimum bandwidth for core (kbps)…✨
struct dpu_pingpong_cfg(9)information of PING-PONG blocks @id enum identifying this block @base register offset of this block✨
struct dpu_plane_state(9)Define dpu extension of drm plane state object✨
struct dpu_pp_blk(9)Pixel processing sub-blk information✨
struct dpu_qos_lut_entry(9)define QoS LUT table entry✨
struct dpu_qos_lut_tbl(9)define QoS LUT table✨
struct dpu_rm(9)DPU dynamic hardware resource manager✨
struct dpu_rotation_cfg(9)define inline rotation config✨
struct dpu_scaler_blk(9)Scaler information✨
struct dpu_sspp_cfg(9)information of source pipes✨
struct dpu_sspp_sub_blks(9)SSPP sub-blocks common: Pointer to common configurations shared by sub blocks✨
struct dpu_sspp_v13_rec_blk(9)SSPP REC sub-blk information✨
struct dpu_sw_pipe(9)software pipe description✨
struct dpu_sw_pipe_cfg(9)software pipe configuration✨
struct dpu_vbif_cfg(9)information of VBIF blocks✨
struct dpu_vbif_dynamic_ot_cfg(9)dynamic OT setting @pps pixel per seconds @ot_limit OT limit to use up to specified pixel per second✨
struct dpu_vbif_dynamic_ot_tbl(9)dynamic OT setting table @count length of cfg @cfg pointer to array of configuration settings with ascending requirements✨
struct dpu_vbif_qos_tbl(9)QoS priority table @npriority_lvl num of priority level @priority_lvl pointer to array of priority level in ascending order✨
struct dpu_vbif_set_qos_params(9)QoS remapper parameter✨
struct dpu_vsync_source_cfg(9)configure vsync source and configure the watchdog timers if required.✨
struct dpu_wb_cfg(9)information of writeback blocks✨
struct drbd_genlmsghdr(9)DRBD specific header used in NETLINK_GENERIC requests✨
struct drm_afbc_framebuffer(9)a special afbc frame buffer object✨
struct drm_amd_vsdb_info(9)AMD-specific VSDB information✨
struct drm_asahi_attachment(9)Describe an "attachment".✨
struct drm_asahi_bg_eot(9)Describe a background or end-of-tile program.✨
struct drm_asahi_cmd_compute(9)Command to submit compute✨
struct drm_asahi_cmd_header(9)Top level command structure✨
struct drm_asahi_cmd_render(9)Command to submit 3D✨
struct drm_asahi_gem_bind_object(9)Arguments passed to DRM_IOCTL_ASAHI_GEM_BIND_OBJECT✨
struct drm_asahi_gem_bind_op(9)Description of a single GEM bind operation.✨
struct drm_asahi_gem_create(9)Arguments passed to DRM_IOCTL_ASAHI_GEM_CREATE✨
struct drm_asahi_gem_mmap_offset(9)Arguments passed to DRM_IOCTL_ASAHI_GEM_MMAP_OFFSET✨
struct drm_asahi_get_params(9)Arguments passed to DRM_IOCTL_ASAHI_GET_PARAMS✨
struct drm_asahi_get_time(9)Arguments passed to DRM_IOCTL_ASAHI_GET_TIME✨
struct drm_asahi_helper_program(9)Describe helper program configuration.✨
struct drm_asahi_params_global(9)Global parameters.✨
struct drm_asahi_queue_create(9)Arguments passed to DRM_IOCTL_ASAHI_QUEUE_CREATE✨
struct drm_asahi_queue_destroy(9)Arguments passed to DRM_IOCTL_ASAHI_QUEUE_DESTROY✨
struct drm_asahi_submit(9)Arguments passed to DRM_IOCTL_ASAHI_SUBMIT✨
struct drm_asahi_sync(9)Sync item✨
struct drm_asahi_timestamp(9)Describe a timestamp write.✨
struct drm_asahi_timestamps(9)Describe timestamp writes.✨
struct drm_asahi_vm_bind(9)Arguments passed to DRM_IOCTL_ASAHI_VM_BIND✨
struct drm_asahi_vm_create(9)Arguments passed to DRM_IOCTL_ASAHI_VM_CREATE✨
struct drm_asahi_vm_destroy(9)Arguments passed to DRM_IOCTL_ASAHI_VM_DESTROY✨
struct drm_asahi_zls_buffer(9)Describe a depth or stencil buffer.✨
struct drm_atomic_commit(9)Atomic commit structure✨
struct drm_atomic_helper_damage_iter(9)Closure structure for damage iterator.✨
struct drm_audio_component(9)Used for direct communication between DRM and hda drivers✨
struct drm_audio_component_audio_ops(9)Ops implemented by hda driver, called by DRM driver✨
struct drm_audio_component_ops(9)Ops implemented by DRM driver, called by hda driver✨
struct drm_bridge(9)central DRM bridge control structure✨
struct drm_bridge_connector(9)A connector backed by a chain of bridges✨
struct drm_bridge_funcs(9)drm_bridge control functions✨
struct drm_bridge_state(9)Atomic bridge state object✨
struct drm_bridge_timings(9)timing information for the bridge✨
struct drm_bus_cfg(9)bus configuration✨
struct drm_client_buffer(9)DRM client buffer✨
struct drm_client_dev(9)DRM client instance✨
struct drm_client_funcs(9)DRM client callbacks✨
struct drm_cmdline_mode(9)DRM Mode passed through the kernel command- line✨
struct drm_colorop(9)DRM color operation control structure✨
struct drm_colorop_funcs(9)driver colorop control functions✨
struct drm_colorop_state(9)mutable colorop state✨
struct drm_connector(9)central DRM connector control structure✨
struct drm_connector_cec(9)DRM Connector CEC-related structure✨
struct drm_connector_cec_funcs(9)drm_hdmi_connector control functions✨
struct drm_connector_funcs(9)control connectors on a given device✨
struct drm_connector_hdmi_audio(9)DRM gemeric HDMI Codec-related structure✨
struct drm_connector_hdmi_funcs(9)drm_hdmi_connector control functions✨
struct drm_connector_hdmi_infoframe(9)HDMI Infoframe container✨
struct drm_connector_helper_funcs(9)helper operations for connectors✨
struct drm_connector_infoframe_funcs(9)InfoFrame-related functions✨
struct drm_connector_list_iter(9)connector_list iterator✨
struct drm_connector_state(9)mutable connector state✨
struct drm_connector_tv_margins(9)TV connector related margins✨
struct drm_crtc(9)central CRTC control structure✨
struct drm_crtc_commit(9)track modeset commits on a CRTC✨
struct drm_crtc_crc(9)data supporting CRC capture on a given CRTC✨
struct drm_crtc_crc_entry(9)entry describing a frame's content✨
struct drm_crtc_funcs(9)control CRTCs for a given device✨
struct drm_crtc_helper_funcs(9)helper operations for CRTCs✨
struct drm_crtc_state(9)mutable CRTC state✨
struct drm_debugfs_entry(9)Per-device debugfs node structure✨
struct drm_debugfs_info(9)debugfs info list entry✨
struct drm_device(9)DRM device structure✨
struct drm_display_info(9)runtime data about the connected sink✨
struct drm_display_mode(9)DRM kernel-internal display mode structure✨
struct drm_dp_as_sdp(9)drm DP Adaptive Sync SDP✨
struct drm_dp_aux(9)DisplayPort AUX channel✨
struct drm_dp_aux_cec(9)DisplayPort CEC-Tunneling-over-AUX✨
struct drm_dp_aux_msg(9)DisplayPort AUX channel transaction✨
struct drm_dp_desc(9)DP branch/sink device descriptor✨
struct drm_dp_link(9)DP link capabilities and configuration✨
struct drm_dp_link_caps(9)DP link capabilities✨
struct drm_dp_link_ops(9)DP link operations✨
struct drm_dp_link_train(9)link training state information✨