STRUCT DPU_HW_CTL(9)

💖 struct dpu_hw_ctl(9) 💖

okay so this is a page from the Kernel API Manual, and we're talking about struct dpu_hw_ctl — literally the CTL PATH driver object. bestie, it's giving main character energy for the display control path, and you're gonna understand it, periodt. 💅

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✨ NAME ✨

struct dpu_hw_ctl — CTL PATH driver object 🎀

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🦋 SYNOPSIS 🦋

struct dpu_hw_ctl {
    struct dpu_hw_blk base;
    struct dpu_hw_blk_reg_map hw;
    int idx;
    const struct dpu_ctl_cfg *caps;
    int mixer_count;
    const struct dpu_lm_cfg *mixer_hw_caps;
    u32 pending_flush_mask;
    u32 pending_intf_flush_mask;
    u32 pending_wb_flush_mask;
    u32 pending_cwb_flush_mask;
    u32 pending_periph_flush_mask;
    u32 pending_merge_3d_flush_mask;
    u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];
    u32 pending_dsc_flush_mask;
    u32 pending_cdm_flush_mask;
    const struct dpu_mdss_version *mdss_ver;
    struct dpu_hw_ctl_ops ops;
 };

like, that's the whole vibe right there ✨ no cap, every field is in there, i didn't skip a single one 🫶

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🌸 Members 🌸

so let's go through the members one by one, bestie, and i promise it's not as scary as it looks 💜

• base — the hardware block base structure, like the foundation of the whole thing 🧱
• hw — the block register map object, iykyk
• idx — the control path index 🔢
• caps — control path capabilities, the whole "what can she do" moment ✨
• mixer_count — number of mixers, literally just the count 🎀
• mixer_hw_caps — mixer hardware capabilities
• pending_flush_mask — storage for pending ctl_flush managed via ops 👑
• pending_intf_flush_mask — pending INTF flush
• pending_wb_flush_mask — pending WB flush
• pending_cwb_flush_mask — pending CWB flush
• pending_periph_flush_mask — pending PERIPH flush
• pending_merge_3d_flush_mask — pending MERGE 3D flush
• pending_dspp_flush_mask — pending DSPP flush
• pending_dsc_flush_mask — pending DSC flush
• pending_cdm_flush_mask — pending CDM flush
• mdss_ver — MDSS revision information, the receipts 📋
• ops — operation list, the whole to-do list of the struct 💅

ngl the flush mask squad is lowkey a lot, but they all live in their own lane and they all matter, so don't skip any of them fr fr 🙈

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🌈 SEE ALSO 🌈

• Kernel file ./drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h enum dpu_ctl_mode_sel(9), struct dpu_hw_stage_cfg(9), struct dpu_hw_intf_cfg(9), struct dpu_hw_ctl_ops(9), to_dpu_hw_ctl(9) ⭐

go read those too, bestie, they're iconic and they're right there 🦋

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and that's the whole page! 🍓 this was written straight from <rainbow>./drivers/gpu/drm/msm/disp/dpu1</rainbow>, dated October 2026, and it's for struct dpu_hw_ctl(9) — slay, you made it to the end, so proud of you 💖✨🎀