STRUCT DPU_HW_INTF_CFG(9)

💅 struct dpu_hw_intf_cfg(9) 💅

okay bestie, welcome to the Kernel API Manual ✨ — this page is all about struct dpu_hw_intf_cfg, and it's literally the glow-up blueprint for how the DPU writes data out to an output interface. no cap, it's giving "control panel for the vibe of your pixels" 🎀

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✨ NAME ✨

struct dpu_hw_intf_cfg — describes how the DPU writes data to the output interface 💖

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🦋 SYNOPSIS 🦋

struct dpu_hw_intf_cfg {
    enum dpu_intf intf;
    enum dpu_intf intf_master;
    enum dpu_wb wb;
    enum dpu_3d_blend_mode mode_3d;
    enum dpu_merge_3d merge_3d;
    enum dpu_ctl_mode_sel intf_mode_sel;
    enum dpu_cdm cdm;
    int stream_sel;
    unsigned int cwb;
    unsigned int dsc;
 };

like, that's the whole squad right there 🫶

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🌸 Members 🌸

time for the member-by-member vibe check, iykyk 👑

• intf — the interface id 🆔
• intf_master — the master interface id in the dual pipe topology, lowkey the main character of the pair 👑
• wb — writeback mode
• mode_3d — the 3d mux configuration
• merge_3d — which 3d merge block is being used
• intf_mode_sel — the interface mode, cmd / vid (pick your fighter 💅)
• cdm — the CDM block used
• stream_sel — stream selection for multi-stream interfaces 🌈
• cwb — the CWB BIT masks used
• dsc — the DSC BIT masks used

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🔥 SEE ALSO 🔥

Kernel file ./drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h enum dpu_ctl_mode_sel(9), struct dpu_hw_stage_cfg(9), struct dpu_hw_ctl_ops(9), struct dpu_hw_ctl(9), to_dpu_hw_ctl(9) — go read the whole friend group, they all ate 💖

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ngl this one lives in ./drivers/gpu/drm/msm/disp/dpu1 and it's stamped October 2026 — that's the source and the date, bestie, so you know exactly where this lore came from 🗓️✨

and that's the page!! slay, you now understand struct dpu_hw_intf_cfg fr fr 🌟💜