STRUCT DPU_HW_CTL_OPS(9)

💖 struct dpu_hw_ctl_ops(9) 💖

🌸 NAME 🌸

okay bestie, this is the Kernel API Manual page for struct dpu_hw_ctl_ops — literally the interface to the wb Hw driver functions. 💅

Assumption is these functions will be called after clocks are enabled. no cap, clocks first, bestie. ✨

✨ SYNOPSIS ✨

       struct dpu_hw_ctl_ops {
           void (*trigger_start)(struct dpu_hw_ctl *ctx);
           bool (*is_started)(struct dpu_hw_ctl *ctx);
           void (*trigger_pending)(struct dpu_hw_ctl *ctx);
           void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);
           u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);
           void (*update_pending_flush)(struct dpu_hw_ctl *ctx, u32 flushbits);
           void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx, enum dpu_wb
       blk);
           void (*update_pending_flush_cwb)(struct dpu_hw_ctl *ctx, enum
       dpu_cwb blk);
           void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx, enum
       dpu_intf blk);
           void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx, enum
       dpu_intf blk);
           void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx, enum
       dpu_merge_3d blk);
           void (*update_pending_flush_sspp)(struct dpu_hw_ctl *ctx, enum
       dpu_sspp blk);
           void (*update_pending_flush_mixer)(struct dpu_hw_ctl *ctx, enum
       dpu_lm blk);
           void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx, enum
       dpu_dspp blk, u32 dspp_sub_blk);
           void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx, enum
       dpu_dsc blk);
           void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum
       dpu_cdm cdm_num);
           void (*trigger_flush)(struct dpu_hw_ctl *ctx);
           u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);
           void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx, struct
       dpu_hw_intf_cfg *cfg);
           void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx, struct
       dpu_hw_intf_cfg *cfg);
           int (*reset)(struct dpu_hw_ctl *c);
           int (*wait_reset_status)(struct dpu_hw_ctl *ctx);
           void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
           void (*setup_blendstage)(struct dpu_hw_ctl *ctx, enum dpu_lm lm,
       struct dpu_hw_stage_cfg *cfg);
           void (*set_active_fetch_pipes)(struct dpu_hw_ctl *ctx, unsigned long
       *fetch_active);
           void (*set_active_pipes)(struct dpu_hw_ctl *ctx, unsigned long
       *active_pipes);
           void (*set_active_lms)(struct dpu_hw_ctl *ctx, unsigned long
       *active_lms);
        };

🎀 Members 🎀

okay bestie, member tour time — all of them, no skips, no “we’ll come back to that later.” 💅

💫 trigger_start

kickoff hw operation for Sw controlled interfaces — DSI cmd mode and WB interface are SW controlled.

• ctx: ctl path ctx pointer.

💫 is_started

check if the ctl is started.

• ctx: ctl path ctx pointer.
• Return: true if started, false if stopped.

💫 trigger_pending

kickoff prepare is in progress hw operation for sw controlled interfaces: DSI cmd mode and WB interface are SW controlled.

• ctx: ctl path ctx pointer.

💫 clear_pending_flush

Clear the value of the cached pending_flush_mask. No effect on hardware. Required to be implemented. like, literally required, bestie 💀

• ctx: ctl path ctx pointer.

💫 get_pending_flush

Query the value of the cached pending_flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.

💫 update_pending_flush

OR in the given flushbits to the cached pending_flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.
• flushbits: module flushmask.

💫 update_pending_flush_wb

OR in the given flushbits to the cached pending_(wb_)flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.
• blk: writeback block index.

💫 update_pending_flush_cwb

OR in the given flushbits to the cached pending_(cwb_)flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.
• blk: concurrent writeback block index.

💫 update_pending_flush_intf

OR in the given flushbits to the cached pending_(intf_)flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.
• blk: interface block index.

💫 update_pending_flush_periph

OR in the given flushbits to the cached pending_(periph_)flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.
• blk: interface block index.

💫 update_pending_flush_merge_3d

OR in the given flushbits to the cached pending_(merge_3d_)flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.
• blk: interface block index.

💫 update_pending_flush_sspp

OR in the given flushbits to the cached pending_flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.
• blk: SSPP block index.

💫 update_pending_flush_mixer

OR in the given flushbits to the cached pending_flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.
• blk: LM block index.

💫 update_pending_flush_dspp

OR in the given flushbits to the cached pending_flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.
• blk: DSPP block index.
• dspp_sub_blk: DSPP sub-block index.

💫 update_pending_flush_dsc

OR in the given flushbits to the cached pending_(dsc_)flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.
• blk: interface block index.

💫 update_pending_flush_cdm

OR in the given flushbits to the cached pending_(cdm_)flush_mask. No effect on hardware.

• ctx: ctl path ctx pointer.
• cdm_num: idx of cdm to be flushed.

💫 trigger_flush

Write the value of the pending_flush_mask to hardware.

• ctx: ctl path ctx pointer.

💫 get_flush_register

Read the value of the flush register.

• ctx: ctl path ctx pointer.
• Return: value of the ctl flush register.

💫 setup_intf_cfg

Setup ctl_path interface config. The parameter note is written as ctx cfg: interface config structure pointer. yes bestie, that’s exactly the note 👀

💫 reset_intf_cfg

reset ctl_path interface config.

• ctx: ctl path ctx pointer.
• cfg: interface config structure pointer.

💫 reset

reset function for this ctl type.

💫 wait_reset_status

checks ctl reset status.

• ctx: ctl path ctx pointer.

This function checks the ctl reset status bit. If the reset bit is set, it keeps polling the status till the hw reset is complete. Returns: 0 on success or -error if reset incomplete within interval.

💫 clear_all_blendstages

Set all blend stages to disabled.

• ctx: ctl path ctx pointer.

💫 setup_blendstage

Configure layer mixer to pipe configuration.

• ctx: ctl path ctx pointer.
• lm: layer mixer enumeration.
• cfg: blend stage configuration.

💫 set_active_fetch_pipes

Set active pipes attached to this CTL.

• ctx: ctl path ctx pointer.
• active_pipes: bitmap of enum dpu_sspp.

💫 set_active_pipes

Set active pipes attached to this CTL.

• ctx: ctl path ctx pointer.
• active_pipes: bitmap of enum dpu_sspp.

💫 set_active_lms

Set active layer mixers attached to this CTL.

• ctx: ctl path ctx pointer.
• active_lms: bitmap of enum dpu_lm.

🌈 SEE ALSO 🌈

Kernel file ./drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:

• enum dpu_ctl_mode_sel(9)
• struct dpu_hw_stage_cfg(9)
• struct dpu_hw_intf_cfg(9)
• struct dpu_hw_ctl(9)
• to_dpu_hw_ctl(9)

---

mwah 💋 bestie, that’s the whole page — source vibe from ./drivers/gpu/drm/msm/disp/dpu1, dated October 2026, all about struct dpu_hw_ctl_ops(9). 🫶✨