STRUCT DPU_ENCODER_VIRT(9)
π struct dpu_encoder_virt(9) β the kernel API manual, but make it make sense
okay so bestie, welcome to the struct dpu_encoder_virt(9) page from the Kernel API Manual π this one lives in ./drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c and honestly? it's giving "main character of the display pipeline" energy, no cap.
β¨ NAME β¨
struct dpu_encoder_virt β the virtual encoder, aka the container of one or more physical encoders. π«Ά
The virtual encoder manages exactly one "logical" display. The physical encoders each manage one intf block, and each one is tied to a specific panel/sub-panel. The virtual encoder defers as much as possible to the physical encoders (she delegates, she's a manager π ), and she registers herself with the DRM Framework as the encoder. Periodt.
π SYNOPSIS π
struct dpu_encoder_virt {
struct drm_encoder base;
spinlock_t enc_spinlock;
bool enabled;
bool commit_done_timedout;
unsigned int num_phys_encs;
struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
struct dpu_encoder_phys *cur_master;
struct dpu_encoder_phys *cur_slave;
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
struct dpu_hw_cwb *hw_cwb[MAX_CWB_PER_ENC];
struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
unsigned int dsc_mask;
unsigned int cwb_mask;
bool intfs_swapped;
struct drm_crtc *crtc;
struct drm_connector *connector;
struct mutex enc_lock;
unsigned long frame_busy_mask[BITS_TO_LONGS(MAX_PHYS_ENCODERS_PER_VIRTUAL)];
atomic_t frame_done_timeout_ms;
atomic_t frame_done_timeout_cnt;
struct timer_list frame_done_timer;
struct msm_display_info disp_info;
bool idle_pc_supported;
struct mutex rc_lock;
enum dpu_enc_rc_states rc_state;
struct delayed_work delayed_off_work;
struct msm_display_topology topology;
u32 idle_timeout;
bool wide_bus_en;
struct drm_dsc_config *dsc;
};
π Members π
okay here's the whole cast, one by one, and yes I'm gonna introduce every single one because they all ate π
baseβ thedrm_encoderbase class, for registration with DRM. literally her legal name for the framework.enc_spinlockβ Virtual-Encoder-Wide Spin Lock for IRQ purposes. one lock to rule the interrupts β¨enabledβTrueif the encoder is active, protected byenc_lock. (emphasis on protected, bestie π)commit_done_timedoutβTrueif there has been a timeout on commit after enabling the encoder. π she timed out, it happens.num_phys_encsβ the actual number of physical encoders contained. the real count, not the vibe count.phys_encsβ the container of physical encoders managed. her whole friend group π«Άcur_masterβ pointer to the current master in this mode. Optimization. Only valid after enable, and cleared as disable. so like, only valid while she's on πcur_slaveβ as above but for the slave encoder. matching set, iconic.hw_ppβ handle to the pingpong blocks used for the display. Ngl, the number of pingpong blocks can be different thannum_phys_encs. don't assume, k?hw_cwbβ handle to the CWB muxes used for concurrent writeback display. The number of CWB muxes can be different thannum_phys_encstoo. same energy as above fr fr.hw_dscβ handle to the DSC blocks used for the display.dsc_maskβ bitmask of used DSC blocks. π―cwb_maskβ bitmask of used CWB muxes.intfs_swappedβ whether or not thephys_encinterfaces have been swapped for partial update right-only cases, such as pingpong split where virtual pingpong does not generate IRQs. (iykyk π)crtcβ pointer to the currently assigned crtc. Normally you would usecrtc->state->encoder_maskto determine the link between encoder/crtc β BUT in this case we need to track crtc in the disable hook, which is called _after_encoder_maskis cleared. so yeah, she has to remember things herself. lowkey relatable.connectorβ if a mode is set, a cached pointer to the active connector. caching queen π§enc_lockβ lock around physical encoder create/destroy/enable/disable. the bouncer at the door.frame_busy_maskβ bitmask tracking whichphys_encwe are still busy processing current command.Bit0 = phys_encs[0]etc.frame_done_timeout_msβ frame done timeout in ms. β±οΈframe_done_timeout_cntβ atomic counter tracking the number of frame done timeouts. yes we're counting them. πframe_done_timerβ watchdog timer for frame done event. she's watching πdisp_infoβ local copy ofmsm_display_infostruct.idle_pc_supportedβ indicate if idle power collaps is supported.rc_lockβ resource control mutex lock to protect virt encoder over various state changes. very demure, very mindful locking.rc_stateβ resource controller state.delayed_off_workβ delayed worker to schedule disabling of clks and resources afterIDLE_TIMEOUTtime. procrastination but make it a feature β¨topologyβ topology of the display. the whole layout, the whole aesthetic πΈidle_timeoutβ idle timeout duration in milliseconds.wide_bus_enβ wide bus is enabled on this interface. wide bus wide vibes πdscβdrm_dsc_configpointer, for DSC-enabled encoders.
π¦ SEE ALSO π¦
the whole squad, in no particular order (okay it's the original order, don't come for me):
- Kernel file
./drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.cenum dpu_enc_rc_events(9) dpu_encoder_get_drm_fmt(9)dpu_encoder_needs_periph_flush(9)dpu_encoder_is_widebus_enabled(9)dpu_encoder_is_dsc_enabled(9)dpu_encoder_get_crc_values_cnt(9)dpu_encoder_setup_misr(9)dpu_encoder_get_crc(9)dpu_encoder_helper_report_irq_timeout(9)dpu_encoder_helper_wait_for_irq(9)dpu_encoder_get_vsync_count(9)dpu_encoder_get_linecount(9)dpu_encoder_helper_split_config(9)dpu_encoder_use_dsc_merge(9)dpu_encoder_get_dsc_config(9)dpu_encoder_prepare_wb_job(9)dpu_encoder_cleanup_wb_job(9)dpu_encoder_virt_runtime_resume(9)dpu_encoder_vblank_callback(9)dpu_encoder_underrun_callback(9)dpu_encoder_assign_crtc(9)dpu_encoder_toggle_vblank_for_crtc(9)dpu_encoder_frame_done_callback(9)_dpu_encoder_trigger_flush(9)_dpu_encoder_trigger_start(9)dpu_encoder_helper_trigger_start(9)_dpu_encoder_kickoff_phys(9)dpu_encoder_trigger_kickoff_pending(9)dpu_encoder_vsync_time(9)dpu_encoder_prepare_for_kickoff(9)dpu_encoder_is_valid_for_commit(9)dpu_encoder_start_frame_done_timer(9)dpu_encoder_kickoff(9)dpu_encoder_helper_phys_cleanup(9)dpu_encoder_helper_phys_setup_cdm(9)dpu_encoder_get_clones(9)dpu_encoder_init(9)dpu_encoder_wait_for_commit_done(9)dpu_encoder_wait_for_tx_complete(9)dpu_encoder_get_intf_mode(9)dpu_encoder_helper_get_cwb_mask(9)dpu_encoder_helper_get_dsc(9)
ngl bestie, this page is from the./drivers/gpu/drm/msm/disp/dpu1directory, dated October 2026, and it's filed understruct dpu_encoder_virt(9). slay π π go read the source, it's right there, ily, bye π«Άβ¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms