STRUCT DPU_HW_INTR(9)

okay bestie, welcome to struct dpu_hw_intr(9) from the Kernel API Manual 💖 this page is literally about the hw interrupts handling data structure, and we're gonna keep every lil' detail intact, fr fr.

🎀 NAME 🎀

struct dpu_hw_intr — the hw interrupts handling data structure. slay.

🌸 SYNOPSIS 🌸

here's the whole struct, bestie — exact vibes, no edits, no cap:

struct dpu_hw_intr {
    struct dpu_hw_blk_reg_map hw;
    u32 cache_irq_mask[MDP_INTR_MAX];
    u32 *save_irq_status;
    spinlock_t irq_lock;
    unsigned long irq_mask;
    const struct dpu_intr_reg *intr_set;
    struct dpu_hw_intr_entry irq_tbl[DPU_NUM_IRQS];
 };

💅 Members 💅

okay so these are the members this page gives their own spotlight ✨

• hw — the virtual address mapping. iconic.
• cache_irq_mask — an array of IRQ enable masks reg storage created during init. yes bestie, that's the whole description.
• save_irq_status — an array of IRQ status reg storage created during init. keeping receipts from init.
• irq_lock — the spinlock for accessing IRQ resources. don't touch the IRQ resources without it, periodt.

also chillin' in the struct, straight from the synopsis above: irq_mask, intr_set, and irq_tbl[DPU_NUM_IRQS] — this Members section doesn't give them separate blurbs, so I'm not out here inventing any 🙈.

🔥 SEE ALSO 🔥

• Kernel file ./drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h — go read it, iykyk 🦋

mwah 💋 cute lil' sign-off: source/version vibes are Kernel API Manual / struct dpu_hw_intr(9), source path ./drivers/gpu/drm/msm/disp/dpu1, dated October 2026. periodt 💖