section 9 · Kernel routines 🧠

87928 pages · page 333 of 440

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S (continued)

struct dmub_rb_cmd_hpd_sense_notify(9)DMUB_OUT_CMD__HPD_SENSE_NOTIFY command.✨
struct dmub_rb_cmd_idle_opt_dcn_notify_idle(9)Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.✨
struct dmub_rb_cmd_idle_opt_dcn_restore(9)DCN restore command data.✨
struct dmub_rb_cmd_idle_opt_set_dc_power_state(9)Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.✨
struct dmub_rb_cmd_mall(9)MALL command data.✨
struct dmub_rb_cmd_panel_cntl(9)Panel control command.✨
struct dmub_rb_cmd_PLAT_54186_wa(9)Underflow workaround command✨
struct dmub_rb_init_params(9)Initialization params for DMUB ringbuffer✨
struct dmub_region(9)dmub hw memory region✨
struct dmub_shared_state_cursor_offload_v1(9)Header metadata for cursor offload.✨
struct dmub_shared_state_feature_block(9)Feature block.✨
struct dmub_shared_state_ips_driver(9)Driver state for IPS.✨
struct dmub_shared_state_ips_fw(9)Firmware state for IPS.✨
struct dmub_soc_fb_info(9)relevant addresses from the frame buffer✨
struct dmub_srv(9)software state for dmcub✨
struct dmub_srv_base_funcs(9)Driver specific base callbacks✨
struct dmub_srv_create_params(9)params for dmub service creation✨
struct dmub_srv_fb_info(9)output fb info from the dmub service✨
struct dmub_srv_fw_meta_info_params(9)params used for fetching fw meta info from fw_image✨
struct dmub_srv_hw_funcs(9)hardware sequencer funcs for dmub✨
struct dmub_srv_memory_params(9)parameters used for driver fb setup✨
struct dmub_srv_region_info(9)output region info from the dmub service✨
struct dmub_srv_region_params(9)params used for calculating dmub regions✨
struct dmub_window(9)dmub hw cache window✨
struct dmx_buffer(9)dmx buffer info✨
struct dmx_demux(9)Structure that contains the demux capabilities and callbacks.✨
struct dmx_exportbuffer(9)export of dmx buffer as DMABUF file descriptor✨
struct dmx_filter(9)Specifies a section header filter.✨
struct dmx_frontend(9)Structure that lists the frontends associated with a demux✨
struct dmx_pes_filter_params(9)Specifies Packetized Elementary Stream (PES) filter parameters.✨
struct dmx_requestbuffers(9)request dmx buffer information✨
struct dmx_sct_filter_params(9)Specifies a section filter.✨
struct dmx_section_feed(9)Structure that contains a section feed filter✨
struct dmx_section_filter(9)Structure that describes a section filter✨
struct dmx_stc(9)Stores System Time Counter (STC) information.✨
struct dmx_ts_feed(9)Structure that contains a TS feed filter✨
struct dmxdev(9)Describes a digital TV demux device.✨
struct dmxdev_feed(9)digital TV dmxdev feed✨
struct dmxdev_filter(9)digital TV dmxdev filter✨
struct do_cleanup_msg(9)The data structure for an SSR do_cleanup message✨
struct docg3(9)DiskOnChip driver private data✨
struct docg3_cascade(9)Cascade of 1 to 4 docg3 chips✨
struct done_ref(9)references that have been done.✨
struct dp_aux_ep_device(9)Main dev structure for DP AUX endpoints✨
struct dp_nlsk_pids(9)array of netlink portids of for a datapath. This is used when OVS_DP_F_DISPATCH_UPCALL_PER_CPU is enabled and must be protected by rcu.✨
struct dp_sdp(9)DP secondary data packet✨
struct dp_sdp_header(9)DP secondary data packet header✨
struct dp_stats_percpu(9)per-cpu packet processing statistics for a given datapath.✨
struct dp_upcall_info(9)metadata to include with a packet sent to userspace✨
struct dpaa2_fd(9)Struct describing FDs✨
struct dpaa2_fl_entry(9)structure for frame list entry.✨
struct dpaa2_io_desc(9)The DPIO descriptor✨
struct dpaa2_io_notification_ctx(9)The DPIO notification context structure✨
struct dpaa2_sg_entry(9)the scatter-gathering structure✨
struct dpbp_attr(9)Structure representing DPBP attributes✨
struct dpcon_attr(9)Structure representing DPCON attributes✨
struct dpcon_notification_cfg(9)Structure representing notification params✨
struct dpdmai_attr(9)Structure representing DPDMAI attributes✨
struct dpdmai_cfg(9)Structure representing DPDMAI configuration✨
struct dpdmai_dest_cfg(9)Structure representing DPDMAI destination parameters✨
struct dpdmai_rx_queue_attr(9)Structure representing attributes of Rx queues✨
struct dpdmai_rx_queue_cfg(9)DPDMAI RX queue configuration✨
struct dpio_attr(9)Structure representing DPIO attributes✨
struct dpio_cfg(9)Structure representing DPIO configuration✨
struct dpkg_extract(9)A structure for defining a single extraction✨
struct dpkg_mask(9)A structure for defining a single extraction mask✨
struct dpkg_profile_cfg(9)A structure for defining a full Key Generation profile (rule)✨
struct dpll_data(9)DPLL registers and integration data✨
struct dpll_device(9)stores DPLL device internal data✨
struct dpll_info(9)display PLL platform specific info✨
struct dpll_pin(9)structure for a dpll pin✨
struct dpll_pin_ref(9)structure for referencing either dpll or pins✨
struct dpmac_attr(9)Structure representing DPMAC attributes✨
struct dpmac_link_state(9)DPMAC link configuration request✨
struct dpni_attr(9)Structure representing DPNI attributes✨
struct dpni_buffer_layout(9)Structure representing DPNI buffer layout✨
struct dpni_congestion_notification_cfg(9)congestion notification configuration✨
struct dpni_dest_cfg(9)Structure representing DPNI destination parameters✨
struct dpni_error_cfg(9)Structure representing DPNI errors treatment✨
struct dpni_fs_action_cfg(9)Action configuration for table look-up✨
struct dpni_fs_tbl_cfg(9)Flow Steering table configuration✨
struct dpni_link_cfg(9)Structure representing DPNI link configuration✨
struct dpni_link_state(9)Structure representing DPNI link state✨
struct dpni_pools_cfg(9)Structure representing buffer pools configuration✨
struct dpni_qos_tbl_cfg(9)Structure representing QOS table configuration✨
struct dpni_queue(9)Queue structure✨
struct dpni_queue_id(9)Queue identification, used for enqueue commands or queue control✨
struct dpni_rule_cfg(9)Rule configuration for table lookup✨
struct dpni_rx_dist_cfg(9)Rx distribution configuration✨
struct dpni_rx_tc_dist_cfg(9)Rx traffic class distribution configuration✨
struct dpni_single_step_cfg(9)configure single step PTP (IEEE 1588)✨
struct dpni_taildrop(9)Structure representing the taildrop✨
struct dpni_tx_shaping_cfg(9)Structure representing DPNI tx shaping configuration✨
struct dpp_color_caps(9)color pipeline capabilities for display pipe and plane blocks✨
struct dprc_attributes(9)Container attributes✨
struct dprc_endpoint(9)Endpoint description for link connect/disconnect operations✨
struct dprc_irq_cfg(9)IRQ configuration✨
struct dprc_region_desc(9)Mappable region descriptor✨
struct dpseci_attr(9)Structure representing DPSECI attributes✨
struct dpseci_cfg(9)Structure representing DPSECI configuration✨
struct dpseci_congestion_notification_cfg(9)congestion notification configuration✨
struct dpseci_dest_cfg(9)Structure representing DPSECI destination parameters✨
struct dpseci_rx_queue_attr(9)Structure representing attributes of Rx queues✨
struct dpseci_rx_queue_cfg(9)DPSECI RX queue configuration✨
struct dpseci_sec_attr(9)Structure representing attributes of the SEC hardware accelerator✨
struct dpseci_tx_queue_attr(9)Structure representing attributes of Tx queues✨
struct dpsw_acl_cfg(9)ACL Configuration✨
struct dpsw_acl_entry_cfg(9)ACL entry✨
struct dpsw_acl_fields(9)ACL fields.✨
struct dpsw_acl_if_cfg(9)List of interfaces to associate with an ACL table✨
struct dpsw_acl_key(9)ACL key✨
struct dpsw_acl_result(9)ACL action✨
struct dpsw_attr(9)Structure representing DPSW attributes✨
struct dpsw_ctrl_if_attr(9)Control interface attributes✨
struct dpsw_ctrl_if_pools_cfg(9)Control interface buffer pools configuration✨
struct dpsw_fdb_attr(9)FDB Attributes✨
struct dpsw_fdb_cfg(9)FDB Configuration✨
struct dpsw_fdb_multicast_cfg(9)Multi-cast entry configuration✨
struct dpsw_fdb_unicast_cfg(9)Unicast entry configuration✨
struct dpsw_if_attr(9)Structure representing DPSW interface attributes✨
struct dpsw_irq_cfg(9)IRQ configuration✨
struct dpsw_lag_cfg(9)Configuration structure for a LAG group✨
struct dpsw_link_cfg(9)Structure representing DPSW link configuration✨
struct dpsw_link_state(9)Structure representing DPSW link state✨
struct dpsw_reflection_cfg(9)Structure representing the mirroring config✨
struct dpsw_stp_cfg(9)Spanning Tree Protocol (STP) Configuration✨
struct dpsw_tci_cfg(9)Tag Control Information (TCI) configuration✨
struct dpsw_vlan_cfg(9)VLAN Configuration✨
struct dpsw_vlan_if_cfg(9)Set of VLAN Interfaces✨
struct dpu_caps(9)define DPU capabilities @max_mixer_width max layer mixer line width support. @max_mixer_blendstages max layer mixer blend stages or supported z order @has_src_split source split feature status…✨
struct dpu_cdm_cfg(9)information of chroma down blocks @name string name for debug purposes @id enum identifying this block @base register offset of this block✨
struct dpu_core_perf(9)definition of core performance context✨
struct dpu_core_perf_params(9)definition of performance parameters✨
struct dpu_core_perf_tune(9)definition of performance tuning control✨
struct dpu_crtc(9)virtualized CRTC data structure✨
struct dpu_crtc_frame_event(9)stores crtc frame event for crtc processing✨
struct dpu_crtc_mixer(9)stores the map for each virtual pipeline in the CRTC✨
struct dpu_crtc_smmu_state_data(9)stores the smmu state and transition type✨
struct dpu_crtc_state(9)dpu container for atomic crtc state✨
struct dpu_danger_safe_status(9)danger and safe status signals✨
struct dpu_drm_de_v1(9)version 1 of detail enhancer structure✨
struct dpu_drm_pix_ext_v1(9)version 1 of pixel ext structure✨
struct dpu_drm_scaler_v2(9)version 2 of struct dpu_drm_scaler✨
struct dpu_dsc_blk(9)DSC Encoder sub-blk information✨
struct dpu_dsc_cfg(9)information of DSC blocks @id enum identifying this block @base register offset of this block✨
struct dpu_dsc_sub_blks(9)DSC sub-blks✨
struct dpu_dspp_cfg(9)information of DSPP blocks @id enum identifying this block @base register offset of this block supported by this block @sblk sub-blocks information✨
struct dpu_dspp_sub_blks(9)Information of DSPP block✨
struct dpu_enc_phys_init_params(9)initialization parameters for phys encs✨
struct dpu_encoder_phys(9)physical encoder that drives a single INTF block tied to a specific panel / sub-panel. Abstract type, sub-classed by phys_vid or phys_cmd for video mode or command mode encs respectively.✨
struct dpu_encoder_phys_cmd(9)sub-class of dpu_encoder_phys to handle command mode specific operations✨
struct dpu_encoder_phys_ops(9)Interface the physical encoders provide to the containing virtual encoder.✨
struct dpu_encoder_phys_wb(9)sub-class of dpu_encoder_phys to handle command mode specific operations✨
struct dpu_encoder_virt(9)virtual encoder. Container of one or more physical encoders. Virtual encoder manages one "logical" display. Physical encoders manage one intf block, tied to a specific panel/sub- panel. Virtual…✨
struct dpu_hw_blk(9)opaque hardware block object✨
struct dpu_hw_cdm(9)cdm description✨
struct dpu_hw_cdm_cfg(9)current configuration of CDM block✨
struct dpu_hw_cdm_ops(9)Interface to the chroma down Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_ctl(9)CTL PATH driver object✨
struct dpu_hw_ctl_ops(9)Interface to the wb Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_cwb(9)CWB mux driver object✨
struct dpu_hw_cwb_ops(9)Interface to the cwb hw driver functions✨
struct dpu_hw_cwb_setup_cfg(9)Describes configuration for CWB mux✨
struct dpu_hw_dither_cfg(9)dither feature structure✨
struct dpu_hw_dsc_ops(9)interface to the dsc hardware driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_dspp(9)dspp description✨
struct dpu_hw_dspp_ops(9)interface to the dspp hardware driver functions Caller must call the init function to get the dspp context for each dspp Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_fmt_layout(9)format information of the source pixel data✨
struct dpu_hw_gc_lut(9)gc lut feature structure✨
struct dpu_hw_intf_cfg(9)Describes how the DPU writes data to output interface✨
struct dpu_hw_intf_ops(9)Interface to the interface Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_intr(9)hw interrupts handling data structure✨
struct dpu_hw_lm_ops(9)Interface to the mixer Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_mdp_ops(9)interface to the MDP TOP Hw driver functions Assumption is these functions will be called after clocks are enabled.✨
struct dpu_hw_merge_3d_ops(9)Interface to the merge_3d Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_pcc_cfg(9)pcc feature structure✨
struct dpu_hw_pcc_coeff(9)PCC coefficient structure for each color component.✨
struct dpu_hw_pingpong_ops(9)Interface to the pingpong Hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_pipe_ts_cfg(9)traffic shaper configuration✨
struct dpu_hw_pp_vsync_info(9)Struct contains parameters to configure read and write pointers for command mode panels✨
struct dpu_hw_qos_cfg(9)pipe QoS configuration✨
struct dpu_hw_scaler3_cfg(9)QSEEDv3 configuration✨
struct dpu_hw_scaler3_de_cfg(9)QSEEDv3 detail enhancer configuration✨
struct dpu_hw_sspp(9)pipe description✨
struct dpu_hw_sspp_ops(9)interface to the SSPP Hw driver functions Caller must call the init function to get the pipe context for each pipe Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_stage_cfg(9)blending stage cfg✨
struct dpu_hw_tear_check(9)Struct contains parameters to configure tear- effect module. This structure is used to configure tear-check logic present either in ping-pong or in interface module.✨
struct dpu_hw_vbif_ops(9)Interface to the VBIF hardware driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_hw_wb(9)WB driver object✨
struct dpu_hw_wb_ops(9)Interface to the wb hw driver functions Assumption is these functions will be called after clocks are enabled✨
struct dpu_intf_cfg(9)information of timing engine blocks @id enum identifying this block @base register offset of this block✨
struct dpu_intr_reg(9)array of DPU register sets✨
struct dpu_lm_cfg(9)information of layer mixer blocks✨
struct dpu_lm_sub_blks(9)information of mixer block✨
struct dpu_mdss_cfg(9)information of MDSS HW This is the main catalog data structure representing this HW version. Contains dpu's major and minor versions, number of instances, register offsets, capabilities of the all…✨
struct dpu_mdss_color(9)mdss color description color 0 : green color 1 : blue color 2 : red color 3 : alpha✨
struct dpu_mdss_version(9)DPU's major and minor versions✨
struct dpu_merge_3d_cfg(9)information of DSPP blocks @id enum identifying this block @base register offset of this block @sblk sub- blocks information✨
struct dpu_perf_cdp_cfg(9)define CDP use case configuration✨
struct dpu_perf_cfg(9)performance control settings @max_bw_low low threshold of maximum bandwidth (kbps) @max_bw_high high threshold of maximum bandwidth (kbps) @min_core_ib minimum bandwidth for core (kbps)…✨