STRUCT DPLL_DATA(9)

🦋 struct dpll_data(9) 🦋

okay bestie, welcome to the Kernel API Manual page for struct dpll_data — literally the DPLL registers and integration data. DPLL? yes. Registers? yes. Integration data? yes. It's giving hardware-core main character energy 👑 and we're gonna walk through every single field together, no cap.

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✨ NAME ✨

struct dpll_data — DPLL registers and integration data 💅

🌸 SYNOPSIS 🌸

okay so here's the whole struct, and yes it's long, but every field is important, periodt:

       struct dpll_data {
           struct clk_omap_reg     mult_div1_reg;
           u32 mult_mask;
           u32 div1_mask;
           struct clk_hw           *clk_bypass;
           struct clk_hw           *clk_ref;
           struct clk_omap_reg     control_reg;
           u32 enable_mask;
           unsigned long           last_rounded_rate;
           u16 last_rounded_m;
           u8 last_rounded_m4xen;
           u8 last_rounded_lpmode;
           u16 max_multiplier;
           u8 last_rounded_n;
           u8 min_divider;
           u16 max_divider;
           unsigned long           max_rate;
           u8 modes;
           struct clk_omap_reg     autoidle_reg;
           struct clk_omap_reg     idlest_reg;
           u32 autoidle_mask;
           u32 freqsel_mask;
           u32 idlest_mask;
           u32 dco_mask;
           u32 sddiv_mask;
           u32 dcc_mask;
           unsigned long           dcc_rate;
           u32 lpmode_mask;
           u32 m4xen_mask;
           u8 auto_recal_bit;
           u8 recal_en_bit;
           u8 recal_st_bit;
           struct clk_omap_reg     ssc_deltam_reg;
           struct clk_omap_reg     ssc_modfreq_reg;
           u32 ssc_deltam_int_mask;
           u32 ssc_deltam_frac_mask;
           u32 ssc_modfreq_mant_mask;
           u32 ssc_modfreq_exp_mask;
           u32 ssc_enable_mask;
           u32 ssc_downspread_mask;
           u32 ssc_modfreq;
           u32 ssc_deltam;
           bool ssc_downspread;
           u8 flags;
        };

🎀 MEMBERS 🎀

okay so here's the entire roster, and yes every one of these is iconic in its own way:

• mult_div1_reg — the register containing the DPLL M and N bitfields 💅
• mult_mask — mask of the DPLL M bitfield in mult_div1_reg ✨
• div1_mask — mask of the DPLL N bitfield in mult_div1_reg
• clk_bypass — struct clk_hw pointer to the clock's bypass clock input 🦋
• clk_ref — struct clk_hw pointer to the clock's reference clock input
• control_reg — register containing the DPLL mode bitfield
• enable_mask — mask of the DPLL mode bitfield in control_reg
• last_rounded_rate — cache of the last rate result of omap2_dpll_determine_rate (iykyk)
• last_rounded_m — cache of the last M result of omap2_dpll_determine_rate
• last_rounded_m4xen — cache of the last M4X result of omap4_dpll_regm4xen_determine_rate
• last_rounded_lpmode — cache of the last lpmode result of omap4_dpll_lpmode_recalc
• max_multiplier — maximum valid non-bypass multiplier value (actual)
• last_rounded_n — cache of the last N result of omap2_dpll_determine_rate
• min_divider — minimum valid non-bypass divider value (actual)
• max_divider — maximum valid non-bypass divider value (actual)
• max_rate — maximum clock rate for the DPLL
• modes — possible values of enable_mask
• autoidle_reg — register containing the DPLL autoidle mode bitfield
• idlest_reg — register containing the DPLL idle status bitfield
• autoidle_mask — mask of the DPLL autoidle mode bitfield in autoidle_reg
• freqsel_mask — mask of the DPLL jitter correction bitfield in control_reg
• idlest_mask — mask of the DPLL idle status bitfield in idlest_reg
• dcc_mask — mask of the DPLL DCC correction bitfield mult_div1_reg
• dcc_rate — rate atleast which DCC dcc_mask must be set (yes, "atleast" is literally what the original says — we're not fixing it 💀)
• lpmode_mask — mask of the DPLL low-power mode bitfield in control_reg
• m4xen_mask — mask of the DPLL M4X multiplier bitfield in control_reg
• auto_recal_bit — bitshift of the driftguard enable bit in control_reg
• recal_en_bit — bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
• recal_st_bit — bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
• ssc_deltam_reg — register containing the DPLL SSC frequency spreading
• ssc_modfreq_reg — register containing the DPLL SSC modulation frequency
• ssc_modfreq_mant_mask — mask of the mantissa component in ssc_modfreq_reg
• ssc_modfreq_exp_mask — mask of the exponent component in ssc_modfreq_reg
• ssc_enable_mask — mask of the DPLL SSC enable bit in control_reg
• ssc_downspread_mask — mask of the DPLL SSC low frequency only bit in control_reg
• ssc_modfreq — the DPLL SSC frequency modulation in kHz
• ssc_deltam — the DPLL SSC frequency spreading in permille (10th of percent)
• ssc_downspread — require the only low frequency spread of the DPLL in SSC mode
• flags — DPLL type/features (see below 👇)

quick heads up bestie: the struct in the synopsis also has dco_mask, sddiv_mask, ssc_deltam_int_mask and ssc_deltam_frac_mask — but the members list doesn't describe them, so we're not gonna invent anything, periodt 💅

🌈 DESCRIPTION 🌈

Possible values for flags: DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) ✨

freqsel_mask is only used on the OMAP34xx family and AM35xx.

XXX Some DPLLs have multiple bypass inputs, so it's not technically correct to only have one clk_bypass pointer. 😭

XXX The runtime-variable fields (last_rounded_rate, last_rounded_m, last_rounded_n) should be separated from the runtime-fixed fields and placed into a different structure, so that the runtime-fixed data can be placed into read-only space. 👑

⭐ SEE ALSO ⭐

• Kernel file ./include/linux/clk/ti.h
• struct clk_omap_reg(9)
• struct clk_hw_omap_ops(9)
• struct clk_hw_omap(9)
• struct ti_clk_ll_ops(9)

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and that's the whole page bestie — Kernel API Manual, source path ./include/linux/clk, dated October 2026. slay 💅✨