STRUCT PVR_PAGE_TABLE_L2_ENTRY_RAW(9)

📦 version 7.3.1, in nixpkgs unstable

💅 struct pvr_page_table_l2_entry_raw(9) — Kernel API Manual 💅

okay so bestie, this is the Kernel API Manual page for a single level-2 page table entry. it's one tiny struct, but the bit layout is lowkey the main character 👑

✨ NAME ✨

struct pvr_page_table_l2_entry_raw — A single entry in a level 2 page table.

🎀 SYNOPSIS 🎀

here's the whole struct, no cap:

struct pvr_page_table_l2_entry_raw {
    u32 val;
 };

🌸 Members 🌸

  • val — The raw value of this entry.

🦋 Description 🦋

This type is a structure for type-checking purposes. At compile-time, its size is checked against ROGUE_MMUCTRL_ENTRY_SIZE_PC_VALUE. like, it's literally there to make the compiler vibe-check the size 💅

The value stored in this structure can be decoded using the following bitmap. the doc's table preamble is FLAT-TABLE: with :widths: 1 5 and :stub-columns: 1 — here's the decoded bit tea so nobody has to squint 🫶

  • 31..4 — Level 1 Page Table Base Address: Bits 39..12 of the L1 page table base address, which is 4KiB aligned.
  • 3..2 — (reserved)
  • 1 — Pending: When valid bit is not set, indicates that a valid entry is pending and the MMU should wait for the driver to map the entry. This is used to support page demand mapping of memory.
  • 0 — Valid: Indicates that the entry contains a valid L1 page table. If the valid bit is not set, then an attempted use of the page would result in a page fault.
bestie, the Valid bit is not decorative — if it's not set, attempting to use the page results in a page fault. periodt 💀

👑 SEE ALSO 👑

Kernel file ./drivers/gpu/drm/imagination/pvr_mmu.c — and the whole friend group is here:

source/version + date sign-off: ./drivers/gpu/drm/imagination · October 2026 · footer tag: struct pvr_p...l2_entry_raw(9). that's the whole page, byeee bestie 🫶💖

📦 where this page comes from