pvr_mmu_op_...require_sync(9)

💖 NAME

Okay so this page is pvr_mmu_op_...require_sync(9) from the Kernel API Manual, and the function it’s hyping up is pvr_mmu_op_context_require_sync.

Here’s the tea, bestie: it marks an MMU op context as requiring a sync operation for the referenced page tables up to a specified level. That’s the whole glow-up. No extra lore, no secret side quests — just marking that sync requirement up to level. ✨

🎀 SYNOPSIS

void pvr_mmu_op_context_require_sync (struct pvr_mmu_op_context *op_ctx
, enum pvr_mmu_sync_level level );

It’s a void function, so no return value to unwrap — it just does the marking thing. 🫶

🌸 ARGUMENTS

• op_ctx — the target MMU op context, aka the thing we’re tagging. 🎯
• level — the maximum page table level for which a sync is required. That’s the ceiling, bestie. 👑

🌈 SEE ALSO

The crossover episode list is, like, iconic and also very long — no skipping any of these, fr fr:

• Kernel file — ./drivers/gpu/drm/imagination/pvr_mmu.c
• pvr_mmu_set_flush_flags(9)
• pvr_mmu_flush_request_all(9)
• pvr_mmu_flush_exec(9)
• PowerVR Virtual Memory Handling(9)
• PowerVR Virtual Memory Handling (constants)(9)
• MMU backing pages(9)
• MMU backing pages (constants)(9)
• struct pvr_mmu_backing_page(9)
• pvr_mmu_backing_page_init(9)
• pvr_mmu_backing_page_fini(9)
• pvr_mmu_backing_page_sync(9)
• Raw page tables(9)
• struct pvr_page_table_l2_entry_raw(9)
• pvr_page_table_l2_entry_raw_set(9)
• struct pvr_page_table_l1_entry_raw(9)
• pvr_page_table_l1_entry_raw_set(9)
• struct pvr_page_table_l0_entry_raw(9)
• struct pvr_page_flags_raw(9)
• pvr_page_table_l0_entry_raw_set(9)
• pvr_page_flags_raw_create(9)
• struct pvr_page_table_l2_raw(9)
• struct pvr_page_table_l1_raw(9)
• struct pvr_page_table_l0_raw(9)
• Mirror page tables(9)
• struct pvr_page_table_l2(9)
• pvr_page_table_l2_init(9)
• pvr_page_table_l2_fini(9)
• pvr_page_table_l2_sync(9)
• pvr_page_table_l2_get_raw(9)
• pvr_page_table_l2_get_entry_raw(9)
• pvr_page_table_l2_entry_is_valid(9)
• struct pvr_page_table_l1(9)
• pvr_page_table_l1_init(9)
• pvr_page_table_l1_free(9)
• pvr_page_table_l1_sync(9)
• pvr_page_table_l1_get_raw(9)
• pvr_page_table_l1_get_entry_raw(9)
• pvr_page_table_l1_entry_is_valid(9)
• struct pvr_page_table_l0(9)
• pvr_page_table_l0_init(9)
• pvr_page_table_l0_free(9)
• pvr_page_table_l0_sync(9)
• pvr_page_table_l0_get_raw(9)
• pvr_page_table_l0_get_entry_raw(9)
• pvr_page_table_l0_entry_is_valid(9)
• struct pvr_mmu_context(9)
• struct pvr_page_table_ptr(9)
• struct pvr_mmu_op_context(9)
• pvr_page_table_l2_insert(9)
• pvr_page_table_l2_remove(9)
• pvr_page_table_l1_insert(9)
• pvr_page_table_l1_remove(9)
• pvr_page_table_l0_insert(9)
• pvr_page_table_l0_remove(9)
• Page table index utilities(9)
• pvr_page_table_l2_idx(9)
• pvr_page_table_l1_idx(9)
• pvr_page_table_l0_idx(9)
• High-level page table operations(9)
• pvr_page_table_l1_get_or_insert(9)
• pvr_page_table_l0_get_or_insert(9)
• pvr_mmu_context_create(9)
• pvr_mmu_context_destroy(9)
• pvr_mmu_get_root_table_dma_addr(9)
• pvr_page_table_l1_alloc(9)
• pvr_page_table_l0_alloc(9)
• pvr_mmu_op_context_sync_manual(9)
• pvr_mmu_op_context_sync_partial(9)
• pvr_mmu_op_context_sync(9)
• pvr_mmu_op_context_load_tables(9)
• pvr_mmu_op_context_set_curr_page(9)
• pvr_mmu_op_context_next_page(9)
• Single page operations(9)
• pvr_page_create(9)
• pvr_page_destroy(9)
• pvr_mmu_op_context_destroy(9)
• pvr_mmu_op_context_create(9)
• pvr_mmu_op_context_unmap_curr_page(9)
• pvr_mmu_unmap(9)
• pvr_mmu_map_sgl(9)
• pvr_mmu_map(9)

Final vibe check, bestie: source/version corner is ./drivers/gpu/drm/imagination, the date on this one is October 2026, and the page is pvr_mmu_op_...require_sync(9). Mwah 💋💅