pvr_page_table_l1_insert(9)

💅 NAME 💅

pvr_page_table_l1_insert(9) — a Kernel API Manual page, bestie, and it's literally about inserting an entry referring to a level 0 page table into a level 1 page table. That's the whole vibe. 💖

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✨ SYNOPSIS ✨

void pvr_page_table_l1_insert (struct pvr_mmu_op_context *op_ctx ,
struct pvr_page_table_l0 *child_table );

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🎀 ARGUMENTS 🎀

• op_ctx — target MMU op context pointing at the entry you're inserting the L0 page table into. 👀
• child_table — the L0 page table to insert. Slay. 🦋

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🧚 DESCRIPTION 🧚

okay so there are exactly two "bestie, that's on you" clauses here, and they are not optional:

Caller job #1: it is the caller's responsibility to ensure op_ctx.curr_page points to a valid L1 entry. ✨

Caller job #2: it is also the caller's responsibility to execute any memory barries (yes, that's the spelling on the page 😭 you know what it means) to ensure that the creation of child_table is ordered before the L1 entry is inserted. Do not skip this, fr fr. 🔥

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🔥 SEE ALSO 🔥

• Kernel file: ./drivers/gpu/drm/imagination/pvr_mmu.c

and the rest of the group chat, no cap:

• pvr_mmu_set_flush_flags(9), pvr_mmu_flush_request_all(9), pvr_mmu_flush_exec(9), PowerVR Virtual Memory Handling(9), PowerVR Virtual Memory Handling (constants)(9)
• MMU backing pages(9), MMU backing pages (constants)(9), struct pvr_mmu_backing_page(9), pvr_mmu_backing_page_init(9), pvr_mmu_backing_page_fini(9), pvr_mmu_backing_page_sync(9)
• Raw page tables(9), struct pvr_page_table_l2_entry_raw(9), pvr_page_table_l2_entry_raw_set(9), struct pvr_page_table_l1_entry_raw(9), pvr_page_table_l1_entry_raw_set(9)
• struct pvr_page_table_l0_entry_raw(9), struct pvr_page_flags_raw(9), pvr_page_table_l0_entry_raw_set(9), pvr_page_flags_raw_create(9)
• struct pvr_page_table_l2_raw(9), struct pvr_page_table_l1_raw(9), struct pvr_page_table_l0_raw(9), Mirror page tables(9)
• struct pvr_page_table_l2(9), pvr_page_table_l2_init(9), pvr_page_table_l2_fini(9), pvr_page_table_l2_sync(9), pvr_page_table_l2_get_raw(9), pvr_page_table_l2_get_entry_raw(9), pvr_page_table_l2_entry_is_valid(9)
• struct pvr_page_table_l1(9), pvr_page_table_l1_init(9), pvr_page_table_l1_free(9), pvr_page_table_l1_sync(9), pvr_page_table_l1_get_raw(9), pvr_page_table_l1_get_entry_raw(9), pvr_page_table_l1_entry_is_valid(9)
• struct pvr_page_table_l0(9), pvr_page_table_l0_init(9), pvr_page_table_l0_free(9), pvr_page_table_l0_sync(9), pvr_page_table_l0_get_raw(9), pvr_page_table_l0_get_entry_raw(9), pvr_page_table_l0_entry_is_valid(9)
• struct pvr_mmu_context(9), struct pvr_page_table_ptr(9), struct pvr_mmu_op_context(9)
• pvr_page_table_l2_insert(9), pvr_page_table_l2_remove(9), pvr_page_table_l1_remove(9), pvr_page_table_l0_insert(9), pvr_page_table_l0_remove(9)
• Page table index utilities(9), pvr_page_table_l2_idx(9), pvr_page_table_l1_idx(9), pvr_page_table_l0_idx(9)
• High-level page table operations(9), pvr_page_table_l1_get_or_insert(9), pvr_page_table_l0_get_or_insert(9)
• pvr_mmu_context_create(9), pvr_mmu_context_destroy(9), pvr_mmu_get_root_table_dma_addr(9), pvr_page_table_l1_alloc(9), pvr_page_table_l0_alloc(9)
• pvr_mmu_op_context_require_sync(9), pvr_mmu_op_context_sync_manual(9), pvr_mmu_op_context_sync_partial(9), pvr_mmu_op_context_sync(9), pvr_mmu_op_context_load_tables(9), pvr_mmu_op_context_set_curr_page(9), pvr_mmu_op_context_next_page(9)
• Single page operations(9), pvr_page_create(9), pvr_page_destroy(9)
• pvr_mmu_op_context_destroy(9), pvr_mmu_op_context_create(9), pvr_mmu_op_context_unmap_curr_page(9), pvr_mmu_unmap(9), pvr_mmu_map_sgl(9), pvr_mmu_map(9)

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okay that's the page!! 💖 source/version: ./drivers/gpu/drm/imagination — date: October 2026. bye bestie, go insert that L0 page table into the L1 page table responsibly 🫶✨