pvr_page_ta...et_entry_raw(9)

pvr_page_table_l0_get_entry_raw(9) ✨ — okay bestie, this is the Kernel API Manual page for accessing an entry from the raw equivalent of a mirror level 0 page table. It’s giving “pointer to a slot, not a promise,” and we’re gonna get into it. 💅

💖 NAME 💖

Access an entry from the raw equivalent of a mirror level 0 page table. That’s the whole vibe: this is the raw-side accessor for a mirror level 0 page table entry. 🫶

✨ SYNOPSIS ✨

struct pvr_page_table_l0_entry_raw * pvr_page_table_l0_get_entry_raw
(struct pvr_page_table_l0 *table , u16 idx );

🎀 ARGUMENTS 🎀

• table — Target level 0 page table. 👑
• idx — Index of the entry to access. 🎯

🦋 DESCRIPTION 🦋

Technically this function returns a pointer to a slot in a raw level 0 page table, since the returned “entry” is not guaranteed to be valid. 😭 Not me handing you a pointer and being like “bestie, please verify.” The caller must verify the validity of the entry at the returned address (perhaps using pvr_page_table_l0_entry_raw_is_valid) before reading or overwriting it.

The value of idx is not checked here; it is the caller’s responsibility to ensure idx refers to a valid index within table before dereferencing the returned pointer. This is especially important for level 0 page tables, which can have a variable number of entries. 🚨 So yeah: vibe check your index, fr fr.

🌸 RETURN 🌸

A pointer to the requested raw level 0 page table entry. periodt. 💖

👑 SEE ALSO 👑

Kernel file and the whole extended universe:

• Kernel file ./drivers/gpu/drm/imagination/pvr_mmu.c
• pvr_mmu_set_flush_flags(9)
• pvr_mmu_flush_request_all(9)
• pvr_mmu_flush_exec(9)
• PowerVR Virtual Memory Handling(9)
• PowerVR Virtual Memory Handling (constants)(9)
• MMU backing pages(9)
• MMU backing pages (constants)(9)
• struct pvr_mmu_backing_page(9)
• pvr_mmu_backing_page_init(9)
• pvr_mmu_backing_page_fini(9)
• pvr_mmu_backing_page_sync(9)
• Raw page tables(9)
• struct pvr_page_table_l2_entry_raw(9)
• pvr_page_table_l2_entry_raw_set(9)
• struct pvr_page_table_l1_entry_raw(9)
• pvr_page_table_l1_entry_raw_set(9)
• struct pvr_page_table_l0_entry_raw(9)
• struct pvr_page_flags_raw(9)
• pvr_page_table_l0_entry_raw_set(9)
• pvr_page_flags_raw_create(9)
• struct pvr_page_table_l2_raw(9)
• struct pvr_page_table_l1_raw(9)
• struct pvr_page_table_l0_raw(9)
• Mirror page tables(9)
• struct pvr_page_table_l2(9)
• pvr_page_table_l2_init(9)
• pvr_page_table_l2_fini(9)
• pvr_page_table_l2_sync(9)
• pvr_page_table_l2_get_raw(9)
• pvr_page_table_l2_get_entry_raw(9)
• pvr_page_table_l2_entry_is_valid(9)
• struct pvr_page_table_l1(9)
• pvr_page_table_l1_init(9)
• pvr_page_table_l1_free(9)
• pvr_page_table_l1_sync(9)
• pvr_page_table_l1_get_raw(9)
• pvr_page_table_l1_get_entry_raw(9)
• pvr_page_table_l1_entry_is_valid(9)
• struct pvr_page_table_l0(9)
• pvr_page_table_l0_init(9)
• pvr_page_table_l0_free(9)
• pvr_page_table_l0_sync(9)
• pvr_page_table_l0_get_raw(9)
• pvr_page_table_l0_entry_is_valid(9)
• struct pvr_mmu_context(9)
• struct pvr_page_table_ptr(9)
• struct pvr_mmu_op_context(9)
• pvr_page_table_l2_insert(9)
• pvr_page_table_l2_remove(9)
• pvr_page_table_l1_insert(9)
• pvr_page_table_l1_remove(9)
• pvr_page_table_l0_insert(9)
• pvr_page_table_l0_remove(9)
• Page table index utilities(9)
• pvr_page_table_l2_idx(9)
• pvr_page_table_l1_idx(9)
• pvr_page_table_l0_idx(9)
• High-level page table operations(9)
• pvr_page_table_l1_get_or_insert(9)
• pvr_page_table_l0_get_or_insert(9)
• pvr_mmu_context_create(9)
• pvr_mmu_context_destroy(9)
• pvr_mmu_get_root_table_dma_addr(9)
• pvr_page_table_l1_alloc(9)
• pvr_page_table_l0_alloc(9)
• pvr_mmu_op_context_require_sync(9)
• pvr_mmu_op_context_sync_manual(9)
• pvr_mmu_op_context_sync_partial(9)
• pvr_mmu_op_context_sync(9)
• pvr_mmu_op_context_load_tables(9)
• pvr_mmu_op_context_set_curr_page(9)
• pvr_mmu_op_context_next_page(9)
• Single page operations(9)
• pvr_page_create(9)
• pvr_page_destroy(9)
• pvr_mmu_op_context_destroy(9)
• pvr_mmu_op_context_create(9)
• pvr_mmu_op_context_unmap_curr_page(9)
• pvr_mmu_unmap(9)
• pvr_mmu_map_sgl(9)
• pvr_mmu_map(9)

this page is from ./drivers/gpu/drm/imagination, dated October 2026, with footer title pvr_page_ta...et_entry_raw(9) — mwah, bye bestie! 💖✨