pvr_page_table_l1_sync(9)
πΈ NAME πΈ
It's pvr_page_table_l1_sync(9) from the Kernel API Manual, bestie, and it's here to flush a level 1 page table from the CPU to the device. That's the whole vibe. π
β¨ SYNOPSIS β¨
void pvr_page_table_l1_sync (struct pvr_page_table_l1 *table );
π ARGUMENTS π
tableβ the target level 1 page table. Yep, that's the one getting the sync treatment. π«Ά
π¦ DESCRIPTION π¦
Okay so this function is literally just a thin wrapper around pvr_mmu_backing_page_sync, which means the warning over there applies here too:
Only callpvr_page_table_l1_synconce you're sure you have no more changes to make totablein the immediate future.
Not me being dramatic, but that warning is doing a lot of heavy lifting. π
Also, if child level 0 page tables of table need to be flushed too, that should be done first using pvr_page_table_l0_sync before calling this function. Order matters, bestie β don't skip the line. π
π SEE ALSO π
Kernel file ./drivers/gpu/drm/imagination/pvr_mmu.c β that's the one. π«‘
The whole linked-up crew:
pvr_mmu_set_flush_flags(9)pvr_mmu_flush_request_all(9)pvr_mmu_flush_exec(9)PowerVR Virtual Memory Handling(9)PowerVR Virtual Memory Handling (constants)(9)MMU backing pages(9)MMU backing pages (constants)(9)struct pvr_mmu_backing_page(9)pvr_mmu_backing_page_init(9)pvr_mmu_backing_page_fini(9)pvr_mmu_backing_page_sync(9)Raw page tables(9)struct pvr_page_table_l2_entry_raw(9)pvr_page_table_l2_entry_raw_set(9)struct pvr_page_table_l1_entry_raw(9)pvr_page_table_l1_entry_raw_set(9)struct pvr_page_table_l0_entry_raw(9)struct pvr_page_flags_raw(9)pvr_page_table_l0_entry_raw_set(9)pvr_page_flags_raw_create(9)struct pvr_page_table_l2_raw(9)struct pvr_page_table_l1_raw(9)struct pvr_page_table_l0_raw(9)Mirror page tables(9)struct pvr_page_table_l2(9)pvr_page_table_l2_init(9)pvr_page_table_l2_fini(9)pvr_page_table_l2_sync(9)pvr_page_table_l2_get_raw(9)pvr_page_table_l2_get_entry_raw(9)pvr_page_table_l2_entry_is_valid(9)struct pvr_page_table_l1(9)pvr_page_table_l1_init(9)pvr_page_table_l1_free(9)pvr_page_table_l1_get_raw(9)pvr_page_table_l1_get_entry_raw(9)pvr_page_table_l1_entry_is_valid(9)struct pvr_page_table_l0(9)pvr_page_table_l0_init(9)pvr_page_table_l0_free(9)pvr_page_table_l0_sync(9)pvr_page_table_l0_get_raw(9)pvr_page_table_l0_get_entry_raw(9)pvr_page_table_l0_entry_is_valid(9)struct pvr_mmu_context(9)struct pvr_page_table_ptr(9)struct pvr_mmu_op_context(9)pvr_page_table_l2_insert(9)pvr_page_table_l2_remove(9)pvr_page_table_l1_insert(9)pvr_page_table_l1_remove(9)pvr_page_table_l0_insert(9)pvr_page_table_l0_remove(9)Page table index utilities(9)pvr_page_table_l2_idx(9)pvr_page_table_l1_idx(9)pvr_page_table_l0_idx(9)High-level page table operations(9)pvr_page_table_l1_get_or_insert(9)pvr_page_table_l0_get_or_insert(9)pvr_mmu_context_create(9)pvr_mmu_context_destroy(9)pvr_mmu_get_root_table_dma_addr(9)pvr_page_table_l1_alloc(9)pvr_page_table_l0_alloc(9)pvr_mmu_op_context_require_sync(9)pvr_mmu_op_context_sync_manual(9)pvr_mmu_op_context_sync_partial(9)pvr_mmu_op_context_sync(9)pvr_mmu_op_context_load_tables(9)pvr_mmu_op_context_set_curr_page(9)pvr_mmu_op_context_next_page(9)Single page operations(9)pvr_page_create(9)pvr_page_destroy(9)pvr_mmu_op_context_destroy(9)pvr_mmu_op_context_create(9)pvr_mmu_op_context_unmap_curr_page(9)pvr_mmu_unmap(9)pvr_mmu_map_sgl(9)pvr_mmu_map(9)
Okay bestie, that's the page β source/version ./drivers/gpu/drm/imagination, dated October 2026, for pvr_page_table_l1_sync(9). Slay. πβ¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms