STRUCT PVR_PAGE_TABLE_L1_ENTRY_RAW(9)

📦 version 7.3.1, in nixpkgs unstable

💅 NAME 💅

okay bestie, welcome to the Kernel API Manual for struct pvr_page_table_l1_entry_raw(9) 💖. This is literally a single entry in a level 1 page table. That's the whole name, no cap.

🌸 SYNOPSIS 🌸

the struct is giving minimal, and the code is exactly:

struct pvr_page_table_l1_entry_raw {
    u64 val;
};

🎀 Members 🎀

  • val — The raw value of this entry. the payload, the tea, the whole thing 💅

🦋 Description 🦋

This type is a structure for type-checking purposes. At compile-time, its size is checked against ROGUE_MMUCTRL_ENTRY_SIZE_PD_VALUE — yes, bestie, the compiler is doing a size vibe check and it is not playing around. 😭

The value stored in this structure can be decoded using the following bitmap:

FLAT-TABLE: the doc's bitmap metadata says :widths: 1 5 and :stub-columns: 1. here's every bit, no skipping:

  • 63..41 — (reserved)
  • 40 — Pending: When valid bit is not set, indicates that a valid entry is pending and the MMU should wait for the driver to map the entry. This is used to support page demand mapping of memory. the MMU is literally waiting on the driver, iconic.
  • 39..5 — Level 0 Page Table Base Address: The way this value is interpreted depends on the page size. Bits not specified in the table below (e.g. bits 11..5 for page size 4KiB) should be considered reserved.

This table shows the bits used in an L1 page table entry to represent the Physical Table Base Address for a given Page Size. Since each L1 page table entry covers 2MiB of address space, the maximum page size is 2MiB.

The nested flat-table metadata is :widths: 1 1 1 1, :header-rows: 1, :stub-columns: 1. The columns are Page size, L0 page table base address bits, Number of L0 page table entries, and Size of L0 page table.

  • Page size 4KiB — L0 page table base address bits: 39..12; number of L0 page table entries: 512; size of L0 page table: 4KiB.
  • Page size 16KiB — L0 page table base address bits: 39..10; number of L0 page table entries: 128; size of L0 page table: 1KiB.
  • Page size 64KiB — L0 page table base address bits: 39..8; number of L0 page table entries: 32; size of L0 page table: 256B.
  • Page size 256KiB — L0 page table base address bits: 39..6; number of L0 page table entries: 8; size of L0 page table: 64B.
  • Page size 1MiB — L0 page table base address bits: 39..5 (4 = '0'); number of L0 page table entries: 2; size of L0 page table: 16B.
  • Page size 2MiB — L0 page table base address bits: 39..5 (4..3 = '00'); number of L0 page table entries: 1; size of L0 page table: 8B.
  • 4 — (reserved)
  • 3..1 — Page Size: Sets the page size, from 4KiB to 2MiB.
  • 0 — Valid: Indicates that the entry contains a valid L0 page table. If the valid bit is not set, then an attempted use of the page would result in a page fault. page fault era avoided, bestie.

👑 SEE ALSO 👑

Kernel file: ./drivers/gpu/drm/imagination/pvr_mmu.c — go look at the source, bestie, it's all there.

made with 💖 from the source ./drivers/gpu/drm/imagination, dated October 2026, and the footer tag is struct pvr_p...l1_entry_raw(9). bye bestie, go slay those page tables 🫶✨

📦 where this page comes from