STRUCT PVR_PAGE_TABLE_L0_ENTRY_RAW(9)

📦 version 7.3.1, in nixpkgs unstable

💖 struct pvr_page_table_l0_entry_raw(9) 💖

okay so you clicked into struct pvr_p...l0_entry_raw(9) — yes bestie, that truncation is literally just how the header renders it, and yes, this is section 9, the Kernel API Manual. buckle up, we're looking at exactly one (1) 64-bit page table entry and honestly? it's giving main character energy. ✨

🌸 NAME

struct pvr_page_table_l0_entry_raw — a single entry in a level 0 page table. that's it. that's the whole vibe. 🎀

✨ SYNOPSIS

struct pvr_page_table_l0_entry_raw {
    u64 val;
 };

look at her. one member. flawless. 💅

🫶 MEMBERS

  • val — the raw value of this entry. the actual bits. the whole personality lives in here. 🔥

🧚 DESCRIPTION

so this type is a structure that exists for type-checking purposes — at compile time, its size gets checked against ROGUE_MMUCTRL_ENTRY_SIZE_PT_VALUE. it's not doing tricks, it's holding the compiler accountable. periodt. 😌

the value stored in this structure can be decoded using the following bitmap 👇

🌈 FLAT-TABLE

(fun fact: the original lays this out as a flat-table with :widths: 1 5 and :stub-columns: 1 — we're translating it into vibes for you 🦋)

  • 63 — (reserved). don't touch. not yours. 🙈
  • 62 — PM/FW Protect: indicates a protected region which only the Parameter Manager (PM) or firmware processor can write to. everyone else? blocked. 💀
  • 61..40 — VP Page (High): virtual-physical page used for Parameter Manager (PM) memory. this field is only used if the additional level of PB virtualization is enabled. the VP Page field is needed by the PM in order to correctly reconstitute the free lists after render completion. this (High) field holds bits 39..18 of the value; the Low field holds bits 17..12. bits 11..0 are always zero because the value is always aligned to the 4KiB page size. she's precise, she's aligned, we stan. 👑
  • 39..12 — Physical Page Address: the way this value is interpreted depends on the page size. bits not specified in the table below (e.g. bits 20..12 for page size 2MiB) should be considered reserved. ⭐

this table shows the bits used in an L0 page table entry to represent the Physical Page Address for a given page size (as defined in the associated L1 page table entry). (another flat-table in the source: :widths: 1 1, :header-rows: 1, :stub-columns: 1 — here it is, cute and flat:)

  • Page size: 4KiB → Physical address bits: 39..12
  • Page size: 16KiB → Physical address bits: 39..14
  • Page size: 64KiB → Physical address bits: 39..16
  • Page size: 256KiB → Physical address bits: 39..18
  • Page size: 1MiB → Physical address bits: 39..20
  • Page size: 2MiB → Physical address bits: 39..21
  • 11..6 — VP Page (Low): continuation of VP Page (High). the sequel. the part two. 🍓
  • 5 — Pending: when the valid bit is not set, indicates that a valid entry is pending and the MMU should wait for the driver to map the entry. this is used to support page demand mapping of memory. yes, the MMU is literally waiting on you. no pressure. 😭
  • 4 — PM Src: set on Parameter Manager (PM) allocated page table entries when indicated by the PM. note that this bit will only be set by the PM, not by the device driver. read that again — only the PM. not the driver. not you. 🫶
  • 3 — SLC Bypass Control: specifies requests to this page should bypass the System Level Cache (SLC), if enabled in SLC configuration. straight past the cache, no detours. 🦋
  • 2 — Cache Coherency: indicates that the page is coherent (i.e. it does not require a cache flush between operations on the CPU and the device). lowkey the most relaxing bit on the whole entry. 💜
  • 1 — Read Only: if set, this bit indicates that the page is read only. an attempted write to this page would result in a write-protection fault. look with your eyes, not with your writes. 👀
  • 0 — Valid: indicates that the entry contains a valid page. if the valid bit is not set, then an attempted use of the page would result in a page fault. this is the bit. the one that matters. 💅

🦋 SEE ALSO

the kernel file lives at ./drivers/gpu/drm/imagination/pvr_mmu.c — and here's the full friend group, every single one of them, no cap:

ngl bestie, if you're poking at these bits by hand, double-check your page size first — misreading the Physical Page Address field is a one-way ticket to a fault, and the reserved bits are reserved for a reason. 🫶

that's the whole page! source and version: ./drivers/gpu/drm/imagination, dated October 2026. go forth and decode your 64 bits responsibly, ily, bye 💖🎀✨

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