drm_dp_pcon_frl_configure_2(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’œ drm_dp_pcon_frl_configure_2(9) πŸ’œ

okay so bestie, welcome to the Kernel API Manual page for drm_dp_pcon_frl_configure_2(9) β€” yes that's a mouthful, yes it's iconic, and yes we're gonna get through it together 🫢


✨ NAME ✨

drm_dp_pcon_frl_configure_2 β€” Set HDMI Link configuration Step-2 πŸŽ€


🌸 SYNOPSIS 🌸

int drm_dp_pcon_frl_configure_2 (struct drm_dp_aux *aux , int
max_frl_mask , u8 frl_type );

like, that's the whole signature, no cap πŸ’…


πŸ¦‹ ARGUMENTS πŸ¦‹

  • aux β€” the DisplayPort AUX channel, bestie. that's the lil chat line our driver uses to talk to stuff ✨
  • max_frl_mask β€” the Max FRL BW to be tried by the PCON with HDMI Sink 🌈 (yes, that's literally what it says, i'm not making this up)
  • frl_type β€” FRL training type, and it can be Extended, or Normal. ok so here's the tea:
    • in Normal FRL training, the PCON tries each frl bw from the max_frl_mask starting from min, and stops when link training is successful πŸ”₯ like it's speedrunning and stopping the second it wins
    • in Extended FRL training, all frl bw selected in the mask are trained by the PCON πŸ‘‘ no skipping, no shortcuts, we do the whole set periodt

🌟 DESCRIPTION 🌟

Returns 0 if success, else returns negative error code. that's it, that's the vibe check β€” zero means slay, negative means πŸ˜­πŸ’€


πŸ‘‘ SEE ALSO πŸ‘‘

Kernel file ./drivers/gpu/drm/display/drm_dp_helper.c dp helpers(9), drm_dp_phy_name(9), drm_dp_lttpr_wake_timeout_setup(9), dp helpers(9), drm_dp_dpcd_probe(9), drm_dp_dpcd_set_powered(9), drm_dp_dpcd_set_probe(9), drm_dp_dpcd_read(9), drm_dp_dpcd_write(9), drm_dp_dpcd_read_link_status(9), drm_dp_dpcd_read_phy_link_status(9), drm_dp_link_power_up(9), drm_dp_link_power_down(9), drm_dp_dpcd_write_payload(9), drm_dp_dpcd_clear_payload(9), drm_dp_dpcd_poll_act_handled(9), drm_dp_downstream_is_type(9), drm_dp_downstream_is_tmds(9), drm_dp_send_real_edid_checksum(9), drm_dp_read_dpcd_caps(9), drm_dp_read_downstream_info(9), drm_dp_downstream_max_dotclock(9), drm_dp_downstream_max_tmds_clock(9), drm_dp_downstream_min_tmds_clock(9), drm_dp_downstream_max_bpc(9), drm_dp_downstream_420_passthrough(9), drm_dp_downstream_444_to_420_conversion(9), drm_dp_downstream_rgb_to_ycbcr_conversion(9), drm_dp_downstream_mode(9), drm_dp_downstream_id(9), drm_dp_downstream_debug(9), drm_dp_subconnector_type(9), drm_dp_set_subconnector_property(9), drm_dp_read_sink_count_cap(9), drm_dp_read_sink_count(9), drm_dp_remote_aux_init(9), drm_dp_aux_init(9), drm_dp_aux_register(9), drm_dp_aux_unregister(9), drm_dp_psr_setup_time(9), drm_dp_start_crc(9), drm_dp_stop_crc(9), drm_dp_read_desc(9), drm_dp_dump_lttpr_desc(9), drm_dp_dsc_sink_bpp_incr(9), drm_dp_dsc_slice_count_to_mask(9), drm_dp_dsc_sink_slice_count_mask(9), drm_dp_dsc_sink_max_slice_count(9), drm_dp_dsc_sink_line_buf_depth(9), drm_dp_dsc_sink_supported_input_bpcs(9), drm_dp_dsc_sink_max_slice_throughput(9), drm_dp_dsc_branch_max_overall_throughput(9), drm_dp_dsc_branch_max_line_width(9), drm_dp_read_lttpr_common_caps(9), drm_dp_read_lttpr_phy_caps(9), drm_dp_lttpr_count(9), drm_dp_lttpr_max_link_rate(9), drm_dp_lttpr_set_transparent_mode(9), drm_dp_lttpr_init(9), drm_dp_lttpr_max_lane_count(9), drm_dp_lttpr_voltage_swing_level_3_supported(9), drm_dp_lttpr_pre_emphasis_level_3_supported(9), drm_dp_get_phy_test_pattern(9), drm_dp_set_phy_test_pattern(9), drm_dp_as_sdp_supported(9), drm_dp_vsc_sdp_supported(9), drm_dp_vsc_sdp_pack(9), drm_dp_get_pcon_max_frl_bw(9), drm_dp_pcon_frl_prepare(9), drm_dp_pcon_is_frl_ready(9), drm_dp_pcon_frl_configure_1(9), drm_dp_pcon_reset_frl_config(9), drm_dp_pcon_frl_enable(9), drm_dp_pcon_hdmi_link_active(9), drm_dp_pcon_hdmi_link_mode(9), drm_dp_pcon_hdmi_frl_link_error_count(9), drm_dp_pcon_pps_default(9), drm_dp_pcon_pps_override_buf(9), drm_edp_backlight_set_level(9), drm_edp_backlight_enable(9), drm_edp_backlight_disable(9), drm_edp_backlight_init(9), drm_panel_dp_aux_backlight(9), drm_dp_link_symbol_cycles(9), drm_dp_bw_overhead(9), drm_dp_bw_channel_coding_efficiency(9), drm_dp_max_dprx_data_rate(9)

like… that's the whole friend group, everyone showed up to the party πŸ§šπŸ’–


and that's the page bestie!! brought to you from ./drivers/gpu/drm/display, dated October 2026, and it's literally titled drm_dp_pcon_frl_configure_2(9) in case you forgot already πŸ™ˆπŸ’œ mwah, go configure some FRL Step-2, ily ⭐

πŸ“¦ where this page comes from