drm_dp_dsc_s...e_throughput(9)
πΈ drm_dp_dsc_sink_max_slice_throughput(9) πΈ
okay bestie, welcome to the Kernel API Manual β yes we're reading kernel docs for fun now, this is who we are π this one's from the drm_dp_helper corner of the DRM world and it's genuinely useful, no cap.
β¨ NAME β¨
drm_dp_dsc_sink_max_slice_throughput β bestie, this hands you the maximum pixel throughput per slice of a DSC sink π like, how much pixel juice can one slice of this thing handle?
π¦ SYNOPSIS π¦
int drm_dp_dsc_sink_max_slice_throughput (const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE] , int peak_pixel_rate , bool
is_rgb_yuv444 );
literally that's the whole signature, copy it exactly, don't be weird about it π
π ARGUMENTS π
dsc_dpcdβ the DSC sink's capabilities, straight out of DPCD β¨ this is the little bundle of self-knowledge the display gives you.peak_pixel_rateβ cumulative peak pixel rate, in kHz. cumulative!! as in, the total for everything hitting the same sink, not just one tile π«Άis_rgb_yuv444β a bool telling you whether the mode is either RGB or YUV444 π (so if it'sfalse, that means yuv422/yuv420, iykyk).
π DESCRIPTION π
so the way this works: it returns the DSC sink device's maximum pixel throughput per slice, and it figures that out from a few things β the device's dsc_dpcd capabilities, the peak_pixel_rate of the transferred stream(s), and whether the output format is_rgb_yuv444 or yuv422/yuv420 π
heads up bestie β peak_pixel_rate is the total pixel rate transferred to the same DSC/display sink. do not come in here with a single-tile number and expect it to slay, it will not fr fr.
for instance, to calculate a tile's slice count of an MST multi-tiled display sink (and we are not considering the required rounding/alignment of slice count here, so don't @ me):
peak_pixel_rate = tile_pixel_rate * tile_count
total_slice_count = peak_pixel_rate / drm_dp_dsc_sink_max_slice_throughput(peak_pixel_rate)
tile_slice_count = total_slice_count / tile_count
see how it eats? π that's the whole flow, iconic.
β RETURN β
it returns the maximum pixel throughput per slice supported by the DSC sink device, in kPixels/sec π« (note: kilo, not the kHz you passed in β stay awake, bestie π).
π SEE ALSO π
go read the whole fam, they're all right there in the kernel file ./drivers/gpu/drm/display/drm_dp_helper.c π§ and also:
dp helpers(9)drm_dp_phy_name(9)drm_dp_lttpr_wake_timeout_setup(9)dp helpers(9)drm_dp_dpcd_probe(9)drm_dp_dpcd_set_powered(9)drm_dp_dpcd_set_probe(9)drm_dp_dpcd_read(9)drm_dp_dpcd_write(9)drm_dp_dpcd_read_link_status(9)drm_dp_dpcd_read_phy_link_status(9)drm_dp_link_power_up(9)drm_dp_link_power_down(9)drm_dp_dpcd_write_payload(9)drm_dp_dpcd_clear_payload(9)drm_dp_dpcd_poll_act_handled(9)drm_dp_downstream_is_type(9)drm_dp_downstream_is_tmds(9)drm_dp_send_real_edid_checksum(9)drm_dp_read_dpcd_caps(9)drm_dp_read_downstream_info(9)drm_dp_downstream_max_dotclock(9)drm_dp_downstream_max_tmds_clock(9)drm_dp_downstream_min_tmds_clock(9)drm_dp_downstream_max_bpc(9)drm_dp_downstream_420_passthrough(9)drm_dp_downstream_444_to_420_conversion(9)drm_dp_downstream_rgb_to_ycbcr_conversion(9)drm_dp_downstream_mode(9)drm_dp_downstream_id(9)drm_dp_downstream_debug(9)drm_dp_subconnector_type(9)drm_dp_set_subconnector_property(9)drm_dp_read_sink_count_cap(9)drm_dp_read_sink_count(9)drm_dp_remote_aux_init(9)drm_dp_aux_init(9)drm_dp_aux_register(9)drm_dp_aux_unregister(9)drm_dp_psr_setup_time(9)drm_dp_start_crc(9)drm_dp_stop_crc(9)drm_dp_read_desc(9)drm_dp_dump_lttpr_desc(9)drm_dp_dsc_sink_bpp_incr(9)drm_dp_dsc_slice_count_to_mask(9)drm_dp_dsc_sink_slice_count_mask(9)drm_dp_dsc_sink_max_slice_count(9)drm_dp_dsc_sink_line_buf_depth(9)drm_dp_dsc_sink_supported_input_bpcs(9)drm_dp_dsc_branch_max_overall_throughput(9)drm_dp_dsc_branch_max_line_width(9)drm_dp_read_lttpr_common_caps(9)drm_dp_read_lttpr_phy_caps(9)drm_dp_lttpr_count(9)drm_dp_lttpr_max_link_rate(9)drm_dp_lttpr_set_transparent_mode(9)drm_dp_lttpr_init(9)drm_dp_lttpr_max_lane_count(9)drm_dp_lttpr_voltage_swing_level_3_supported(9)drm_dp_lttpr_pre_emphasis_level_3_supported(9)drm_dp_get_phy_test_pattern(9)drm_dp_set_phy_test_pattern(9)drm_dp_as_sdp_supported(9)drm_dp_vsc_sdp_supported(9)drm_dp_vsc_sdp_pack(9)drm_dp_get_pcon_max_frl_bw(9)drm_dp_pcon_frl_prepare(9)drm_dp_pcon_is_frl_ready(9)drm_dp_pcon_frl_configure_1(9)drm_dp_pcon_frl_configure_2(9)drm_dp_pcon_reset_frl_config(9)drm_dp_pcon_frl_enable(9)drm_dp_pcon_hdmi_link_active(9)drm_dp_pcon_hdmi_link_mode(9)drm_dp_pcon_hdmi_frl_link_error_count(9)drm_dp_pcon_pps_default(9)drm_dp_pcon_pps_override_buf(9)drm_edp_backlight_set_level(9)drm_edp_backlight_enable(9)drm_edp_backlight_disable(9)drm_edp_backlight_init(9)drm_panel_dp_aux_backlight(9)drm_dp_link_symbol_cycles(9)drm_dp_bw_overhead(9)drm_dp_bw_channel_coding_efficiency(9)drm_dp_max_dprx_data_rate(9)
and that's the page, bestie π«Ά this whole vibe lives at ./drivers/gpu/drm/display, it's dated October 2026, and yeah the page title in the corner is that truncated little drm_dp_dsc_s...e_throughput(9) moment β she got cut off but she's still iconic ππ bye luv u, go read your DPCD β¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms