drm_dp_pcon_frl_configure_1(9)

okay bestie, welcome to the drm_dp_pcon_frl_configure_1(9) page from the Kernel API Manual 🌈 — we're doing HDMI FRL link setup, group-chat style, but every technical detail is staying exactly where it belongs. periodt 💅

💖 NAME 💖

drm_dp_pcon_frl_configure_1 - Set HDMI LINK Configuration-Step1

✨ SYNOPSIS ✨

int drm_dp_pcon_frl_configure_1 (struct drm_dp_aux *aux , int
       max_frl_gbps , u8 frl_mode );

🎀 ARGUMENTS 🎀

• aux — DisplayPort AUX channel, the literal DP AUX channel bestie 💬
• max_frl_gbps — maximum frl bw to be configured between PCON and HDMI sink 🌸
• frl_mode — FRL Training mode, it can be either Concurrent or Sequential. In Concurrent Mode, the FRL link bring up can be done along with DP Link training. In Sequential mode, the FRL link bring up is done prior to the DP Link training. 👑

🦋 DESCRIPTION 🦋

Returns 0 if success, else returns negative error code. That's the whole vibe: success hands you 0, and anything else comes back as a negative error code 😭.

🔗 SEE ALSO 🔗

Kernel file ./drivers/gpu/drm/display/drm_dp_helper.c, dp helpers(9), drm_dp_phy_name(9), drm_dp_lttpr_wake_timeout_setup(9), dp helpers(9), drm_dp_dpcd_probe(9), drm_dp_dpcd_set_powered(9), drm_dp_dpcd_set_probe(9), drm_dp_dpcd_read(9), drm_dp_dpcd_write(9), drm_dp_dpcd_read_link_status(9), drm_dp_dpcd_read_phy_link_status(9), drm_dp_link_power_up(9), drm_dp_link_power_down(9), drm_dp_dpcd_write_payload(9), drm_dp_dpcd_clear_payload(9), drm_dp_dpcd_poll_act_handled(9), drm_dp_downstream_is_type(9), drm_dp_downstream_is_tmds(9), drm_dp_send_real_edid_checksum(9), drm_dp_read_dpcd_caps(9), drm_dp_read_downstream_info(9), drm_dp_downstream_max_dotclock(9), drm_dp_downstream_max_tmds_clock(9), drm_dp_downstream_min_tmds_clock(9), drm_dp_downstream_max_bpc(9), drm_dp_downstream_420_passthrough(9), drm_dp_downstream_444_to_420_conversion(9), drm_dp_downstream_rgb_to_ycbcr_conversion(9), drm_dp_downstream_mode(9), drm_dp_downstream_id(9), drm_dp_downstream_debug(9), drm_dp_subconnector_type(9), drm_dp_set_subconnector_property(9), drm_dp_read_sink_count_cap(9), drm_dp_read_sink_count(9), drm_dp_remote_aux_init(9), drm_dp_aux_init(9), drm_dp_aux_register(9), drm_dp_aux_unregister(9), drm_dp_psr_setup_time(9), drm_dp_start_crc(9), drm_dp_stop_crc(9), drm_dp_read_desc(9), drm_dp_dump_lttpr_desc(9), drm_dp_dsc_sink_bpp_incr(9), drm_dp_dsc_slice_count_to_mask(9), drm_dp_dsc_sink_slice_count_mask(9), drm_dp_dsc_sink_max_slice_count(9), drm_dp_dsc_sink_line_buf_depth(9), drm_dp_dsc_sink_supported_input_bpcs(9), drm_dp_dsc_sink_max_slice_throughput(9), drm_dp_dsc_branch_max_overall_throughput(9), drm_dp_dsc_branch_max_line_width(9), drm_dp_read_lttpr_common_caps(9), drm_dp_read_lttpr_phy_caps(9), drm_dp_lttpr_count(9), drm_dp_lttpr_max_link_rate(9), drm_dp_lttpr_set_transparent_mode(9), drm_dp_lttpr_init(9), drm_dp_lttpr_max_lane_count(9), drm_dp_lttpr_voltage_swing_level_3_supported(9), drm_dp_lttpr_pre_emphasis_level_3_supported(9), drm_dp_get_phy_test_pattern(9), drm_dp_set_phy_test_pattern(9), drm_dp_as_sdp_supported(9), drm_dp_vsc_sdp_supported(9), drm_dp_vsc_sdp_pack(9), drm_dp_get_pcon_max_frl_bw(9), drm_dp_pcon_frl_prepare(9), drm_dp_pcon_is_frl_ready(9), drm_dp_pcon_frl_configure_2(9), drm_dp_pcon_reset_frl_config(9), drm_dp_pcon_frl_enable(9), drm_dp_pcon_hdmi_link_active(9), drm_dp_pcon_hdmi_link_mode(9), drm_dp_pcon_hdmi_frl_link_error_count(9), drm_dp_pcon_pps_default(9), drm_dp_pcon_pps_override_buf(9), drm_edp_backlight_set_level(9), drm_edp_backlight_enable(9), drm_edp_backlight_disable(9), drm_edp_backlight_init(9), drm_panel_dp_aux_backlight(9), drm_dp_link_symbol_cycles(9), drm_dp_bw_overhead(9), drm_dp_bw_channel_coding_efficiency(9), drm_dp_max_dprx_data_rate(9)

mwah 💋 source/version: ./drivers/gpu/drm/display; date stamp: October 2026; page: drm_dp_pcon_frl_configure_1(9). bye bestie, go configure that FRL like the icon you are 🫶✨