drm_dp_dsc_s...e_count_mask(9)
okay so bestie, welcome to the Kernel API Manual page for drm_dp_dsc_s...e_count_mask(9) β¨ yes that's literally the name up top β the header squishes it down with the little ... in the middle, and we're leaving it exactly like that because that's how the page is filed π
(the NAME section below spells the whole thing out for you, iykyk).
πΈ NAME πΈ
drm_dp_dsc_sink_slice_count_mask β get the mask of valid DSC sink slice counts π₯
β¨ SYNOPSIS β¨
u32 drm_dp_dsc_sink_slice_count_mask (const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE] , bool is_edp );
π ARGUMENTS π
dsc_dpcdβ the sink's DSC DPCD capabilities. this is the little blob of capability data you're handin over π«Άis_edpβtruefor an eDP sink (so, like, a laptop-panel situation, not a regular external display vibe) π
π¦ DESCRIPTION π¦
okay so what this actually does: it goes and grabs the mask of supported slice counts straight out of the sink's DSC DPCD register β¨ lowkey it's just a "hey, what slice counts can you do?" lookup, and it hands you back a mask instead of a list. that's the whole thing. no cap, that's it π
β RETURN β
mask of slice counts supported by the DSC sink, and here's how to read it:
> 0β bit#0,1,3,5..,23 set if the sink supports 1,2,4,6..,24 slices π0β if the sink doesn't support any slices π
fr fr, watch those bit positions βbit#0,1,3,5..,23is not a straight1,2,3,4walk, it's the real deal exactly as written. don't be out here assuming π
π SEE ALSO π
the kernel file behind all this: ./drivers/gpu/drm/display/drm_dp_helper.c π
and now, the full friend group β every single one, no skipping, because the manpage said so and we don't gatekeep here π«Ά (and yes, dp helpers(9) shows up twice in the list, that's literally how the page has it, we're not editing the icon's choices π
):
dp helpers(9)drm_dp_phy_name(9)drm_dp_lttpr_wake_timeout_setup(9)dp helpers(9)drm_dp_dpcd_probe(9)drm_dp_dpcd_set_powered(9)drm_dp_dpcd_set_probe(9)drm_dp_dpcd_read(9)drm_dp_dpcd_write(9)drm_dp_dpcd_read_link_status(9)drm_dp_dpcd_read_phy_link_status(9)drm_dp_link_power_up(9)drm_dp_link_power_down(9)drm_dp_dpcd_write_payload(9)drm_dp_dpcd_clear_payload(9)drm_dp_dpcd_poll_act_handled(9)drm_dp_downstream_is_type(9)drm_dp_downstream_is_tmds(9)drm_dp_send_real_edid_checksum(9)drm_dp_read_dpcd_caps(9)drm_dp_read_downstream_info(9)drm_dp_downstream_max_dotclock(9)drm_dp_downstream_max_tmds_clock(9)drm_dp_downstream_min_tmds_clock(9)drm_dp_downstream_max_bpc(9)drm_dp_downstream_420_passthrough(9)drm_dp_downstream_444_to_420_conversion(9)drm_dp_downstream_rgb_to_ycbcr_conversion(9)drm_dp_downstream_mode(9)drm_dp_downstream_id(9)drm_dp_downstream_debug(9)drm_dp_subconnector_type(9)drm_dp_set_subconnector_property(9)drm_dp_read_sink_count_cap(9)drm_dp_read_sink_count(9)drm_dp_remote_aux_init(9)drm_dp_aux_init(9)drm_dp_aux_register(9)drm_dp_aux_unregister(9)drm_dp_psr_setup_time(9)drm_dp_start_crc(9)drm_dp_stop_crc(9)drm_dp_read_desc(9)drm_dp_dump_lttpr_desc(9)drm_dp_dsc_sink_bpp_incr(9)drm_dp_dsc_slice_count_to_mask(9)drm_dp_dsc_sink_max_slice_count(9)drm_dp_dsc_sink_line_buf_depth(9)drm_dp_dsc_sink_supported_input_bpcs(9)drm_dp_dsc_sink_max_slice_throughput(9)drm_dp_dsc_branch_max_overall_throughput(9)drm_dp_dsc_branch_max_line_width(9)drm_dp_read_lttpr_common_caps(9)drm_dp_read_lttpr_phy_caps(9)drm_dp_lttpr_count(9)drm_dp_lttpr_max_link_rate(9)drm_dp_lttpr_set_transparent_mode(9)drm_dp_lttpr_init(9)drm_dp_lttpr_max_lane_count(9)drm_dp_lttpr_voltage_swing_level_3_supported(9)drm_dp_lttpr_pre_emphasis_level_3_supported(9)drm_dp_get_phy_test_pattern(9)drm_dp_set_phy_test_pattern(9)drm_dp_as_sdp_supported(9)drm_dp_vsc_sdp_supported(9)drm_dp_vsc_sdp_pack(9)drm_dp_get_pcon_max_frl_bw(9)drm_dp_pcon_frl_prepare(9)drm_dp_pcon_is_frl_ready(9)drm_dp_pcon_frl_configure_1(9)drm_dp_pcon_frl_configure_2(9)drm_dp_pcon_reset_frl_config(9)drm_dp_pcon_frl_enable(9)drm_dp_pcon_hdmi_link_active(9)drm_dp_pcon_hdmi_link_mode(9)drm_dp_pcon_hdmi_frl_link_error_count(9)drm_dp_pcon_pps_default(9)drm_dp_pcon_pps_override_buf(9)drm_edp_backlight_set_level(9)drm_edp_backlight_enable(9)drm_edp_backlight_disable(9)drm_edp_backlight_init(9)drm_panel_dp_aux_backlight(9)drm_dp_link_symbol_cycles(9)drm_dp_bw_overhead(9)drm_dp_bw_channel_coding_efficiency(9)drm_dp_max_dprx_data_rate(9)
that's the page, bestie, you ate it π and for the cute sign-off: this one lives under source ./drivers/gpu/drm/display, dated October 2026, and if you ever need to find it again it's filed right back under drm_dp_dsc_s...e_count_mask(9) where it belongs π§π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms