drm_dp_dsc_b...x_line_width(9)
β¨ drm_dp_dsc_branch_max_line_width β¨
okay so bestie, welcome to the Kernel API Manual page for drm_dp_dsc_branch_max_line_width(9) β yes the header up top is literally rendered as drm_dp_dsc_b...x_line_width(9) because terminals are dramatic and truncate things, but we know her full name and we're gonna say it with our whole chest π
πΈ NAME πΈ
drm_dp_dsc_branch_max_line_width β the branch device's max DSC line width, that's the whole vibe π«Ά
π SYNOPSIS π
int drm_dp_dsc_branch_max_line_width (const u8
dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE] );
literally that's it. one function, one array, zero drama β¨
π¦ ARGUMENTS π¦
dsc_branch_dpcdβ the DSC branch capabilities straight out of DPCD, bestie π
π₯ DESCRIPTION π₯
so what does she do? she returns the branch device's maximum overall DSC line width, and she figures it out based on the device's own dsc_branch_dpcd capabilities. it's giving "read the flex, report the flex" ππ
no cap, that's the entire description. she's a one-job icon and she ate.
π RETURN π
bestie the return values are a whole personality test, look:
0β the max line width is not indicated by the device separately, so it has to be determined from the maximum slice count and slice-width supported by the device. iykyk, you gotta derive it yourself π§-EINVALβ the device is being messy and indicates an invalid maximum line width (< 5120pixels). invalid. not the vibe. π>= 5120β slay, that's the max line width in pixels βπ
lowkey important: 0 is not an error, it's a "go do the math with slice count and slice-width" situation. don't be out here treating it like a failure fr fr π
π SEE ALSO π
this list is long long, so buckle up bestie. all of these are from the kernel file ./drivers/gpu/drm/display/drm_dp_helper.c β the dp helpers zone β and here's the full squad in order:
dp helpers(9),drm_dp_phy_name(9),drm_dp_lttpr_wake_timeout_setup(9),dp helpers(9),drm_dp_dpcd_probe(9),drm_dp_dpcd_set_powered(9),drm_dp_dpcd_set_probe(9),drm_dp_dpcd_read(9),drm_dp_dpcd_write(9),drm_dp_dpcd_read_link_status(9),drm_dp_dpcd_read_phy_link_status(9),drm_dp_link_power_up(9),drm_dp_link_power_down(9)drm_dp_dpcd_write_payload(9),drm_dp_dpcd_clear_payload(9),drm_dp_dpcd_poll_act_handled(9),drm_dp_downstream_is_type(9),drm_dp_downstream_is_tmds(9),drm_dp_send_real_edid_checksum(9),drm_dp_read_dpcd_caps(9),drm_dp_read_downstream_info(9),drm_dp_downstream_max_dotclock(9),drm_dp_downstream_max_tmds_clock(9),drm_dp_downstream_min_tmds_clock(9),drm_dp_downstream_max_bpc(9),drm_dp_downstream_420_passthrough(9)drm_dp_downstream_444_to_420_conversion(9),drm_dp_downstream_rgb_to_ycbcr_conversion(9),drm_dp_downstream_mode(9),drm_dp_downstream_id(9),drm_dp_downstream_debug(9),drm_dp_subconnector_type(9),drm_dp_set_subconnector_property(9),drm_dp_read_sink_count_cap(9),drm_dp_read_sink_count(9),drm_dp_remote_aux_init(9),drm_dp_aux_init(9),drm_dp_aux_register(9),drm_dp_aux_unregister(9)drm_dp_psr_setup_time(9),drm_dp_start_crc(9),drm_dp_stop_crc(9),drm_dp_read_desc(9),drm_dp_dump_lttpr_desc(9),drm_dp_dsc_sink_bpp_incr(9),drm_dp_dsc_slice_count_to_mask(9),drm_dp_dsc_sink_slice_count_mask(9),drm_dp_dsc_sink_max_slice_count(9),drm_dp_dsc_sink_line_buf_depth(9),drm_dp_dsc_sink_supported_input_bpcs(9),drm_dp_dsc_sink_max_slice_throughput(9),drm_dp_dsc_branch_max_overall_throughput(9)drm_dp_read_lttpr_common_caps(9),drm_dp_read_lttpr_phy_caps(9),drm_dp_lttpr_count(9),drm_dp_lttpr_max_link_rate(9),drm_dp_lttpr_set_transparent_mode(9),drm_dp_lttpr_init(9),drm_dp_lttpr_max_lane_count(9),drm_dp_lttpr_voltage_swing_level_3_supported(9),drm_dp_lttpr_pre_emphasis_level_3_supported(9),drm_dp_get_phy_test_pattern(9),drm_dp_set_phy_test_pattern(9)drm_dp_as_sdp_supported(9),drm_dp_vsc_sdp_supported(9),drm_dp_vsc_sdp_pack(9),drm_dp_get_pcon_max_frl_bw(9),drm_dp_pcon_frl_prepare(9),drm_dp_pcon_is_frl_ready(9),drm_dp_pcon_frl_configure_1(9),drm_dp_pcon_frl_configure_2(9),drm_dp_pcon_reset_frl_config(9),drm_dp_pcon_frl_enable(9),drm_dp_pcon_hdmi_link_active(9),drm_dp_pcon_hdmi_link_mode(9),drm_dp_pcon_hdmi_frl_link_error_count(9)drm_dp_pcon_pps_default(9),drm_dp_pcon_pps_override_buf(9),drm_edp_backlight_set_level(9),drm_edp_backlight_enable(9),drm_edp_backlight_disable(9),drm_edp_backlight_init(9),drm_panel_dp_aux_backlight(9),drm_dp_link_symbol_cycles(9),drm_dp_bw_overhead(9),drm_dp_bw_channel_coding_efficiency(9),drm_dp_max_dprx_data_rate(9)
like I said. the whole squad. she knows everyone ππ
and that's the page bestie!! π source is ./drivers/gpu/drm/display, version October 2026, Kernel API Manual β mwah, go read some DPCD, ily, bye π¦π
β¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms