drm_dp_dsc_b...l_throughput(9)

✨ drm_dp_dsc_branch_max_overall_throughput(9) ✨

okay so bestie, we're in the Kernel API Manual today (yes, that one 💅) and this little icon is called drm_dp_dsc_branch_max_overall_throughput — it's giving "how much DSC pixel throughput can this branch device actually handle" energy 🔥

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🌸 NAME 🌸

drm_dp_dsc_branch_max_overall_throughput — literally just returns the branch device's max overall DSC pixel throughput. no cap 🫶

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🦋 SYNOPSIS 🦋

int drm_dp_dsc_branch_max_overall_throughput (const u8
       dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE] , bool is_rgb_yuv444 );

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🎀 ARGUMENTS 🎀

• dsc_branch_dpcd — the DSC branch capabilities, straight outta DPCD 💖
• is_rgb_yuv444 — tells us whether the mode is either RGB or YUV444 (the icon needs the tea so it knows which flavor of format we're on ✨)

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💅 DESCRIPTION 💅

So bestie, what this does is return the branch device's maximum overall DSC pixel throughput, based on two things:

1. the device's DPCD DSC branch capabilities (dsc_branch_dpcd), and
2. whether the output format is is_rgb_yuv444 or yuv422/yuv420 👑

that's the whole vibe. it's reading the caps and doing the math for you, periodt.

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🌈 RETURN 🌈

• 0 — waittt, a zero 😭 ok so this means the maximum overall throughput capability is not indicated by the device separately, and it must be determined from the per-slice max throughput (see drm_dp_dsc_branch_slice_max_throughput) and the maximum slice count supported by the device. lowkey you gotta do the extra homework, sorry bestie 🫠
• > 0 — slayyy 💖 this is the maximum overall DSC pixel throughput supported by the branch device, in kPixels/sec ✨ (yes, kilo-pixels per second, we stay metric in this house)

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👑 SEE ALSO 👑

kernel file ./drivers/gpu/drm/display/drm_dp_helper.c 🔥 and all these icons, in the exact order the universe intended: dp helpers(9), drm_dp_phy_name(9), drm_dp_lttpr_wake_timeout_setup(9), dp helpers(9), drm_dp_dpcd_probe(9), drm_dp_dpcd_set_powered(9), drm_dp_dpcd_set_probe(9), drm_dp_dpcd_read(9), drm_dp_dpcd_write(9), drm_dp_dpcd_read_link_status(9), drm_dp_dpcd_read_phy_link_status(9), drm_dp_link_power_up(9), drm_dp_link_power_down(9), drm_dp_dpcd_write_payload(9), drm_dp_dpcd_clear_payload(9), drm_dp_dpcd_poll_act_handled(9), drm_dp_downstream_is_type(9), drm_dp_downstream_is_tmds(9), drm_dp_send_real_edid_checksum(9), drm_dp_read_dpcd_caps(9), drm_dp_read_downstream_info(9), drm_dp_downstream_max_dotclock(9), drm_dp_downstream_max_tmds_clock(9), drm_dp_downstream_min_tmds_clock(9), drm_dp_downstream_max_bpc(9), drm_dp_downstream_420_passthrough(9), drm_dp_downstream_444_to_420_conversion(9), drm_dp_downstream_rgb_to_ycbcr_conversion(9), drm_dp_downstream_mode(9), drm_dp_downstream_id(9), drm_dp_downstream_debug(9), drm_dp_subconnector_type(9), drm_dp_set_subconnector_property(9), drm_dp_read_sink_count_cap(9), drm_dp_read_sink_count(9), drm_dp_remote_aux_init(9), drm_dp_aux_init(9), drm_dp_aux_register(9), drm_dp_aux_unregister(9), drm_dp_psr_setup_time(9), drm_dp_start_crc(9), drm_dp_stop_crc(9), drm_dp_read_desc(9), drm_dp_dump_lttpr_desc(9), drm_dp_dsc_sink_bpp_incr(9), drm_dp_dsc_slice_count_to_mask(9), drm_dp_dsc_sink_slice_count_mask(9), drm_dp_dsc_sink_max_slice_count(9), drm_dp_dsc_sink_line_buf_depth(9), drm_dp_dsc_sink_supported_input_bpcs(9), drm_dp_dsc_sink_max_slice_throughput(9), drm_dp_dsc_branch_max_line_width(9), drm_dp_read_lttpr_common_caps(9), drm_dp_read_lttpr_phy_caps(9), drm_dp_lttpr_count(9), drm_dp_lttpr_max_link_rate(9), drm_dp_lttpr_set_transparent_mode(9), drm_dp_lttpr_init(9), drm_dp_lttpr_max_lane_count(9), drm_dp_lttpr_voltage_swing_level_3_supported(9), drm_dp_lttpr_pre_emphasis_level_3_supported(9), drm_dp_get_phy_test_pattern(9), drm_dp_set_phy_test_pattern(9), drm_dp_as_sdp_supported(9), drm_dp_vsc_sdp_supported(9), drm_dp_vsc_sdp_pack(9), drm_dp_get_pcon_max_frl_bw(9), drm_dp_pcon_frl_prepare(9), drm_dp_pcon_is_frl_ready(9), drm_dp_pcon_frl_configure_1(9), drm_dp_pcon_frl_configure_2(9), drm_dp_pcon_reset_frl_config(9), drm_dp_pcon_frl_enable(9), drm_dp_pcon_hdmi_link_active(9), drm_dp_pcon_hdmi_link_mode(9), drm_dp_pcon_hdmi_frl_link_error_count(9), drm_dp_pcon_pps_default(9), drm_dp_pcon_pps_override_buf(9), drm_edp_backlight_set_level(9), drm_edp_backlight_enable(9), drm_edp_backlight_disable(9), drm_edp_backlight_init(9), drm_panel_dp_aux_backlight(9), drm_dp_link_symbol_cycles(9), drm_dp_bw_overhead(9), drm_dp_bw_channel_coding_efficiency(9), drm_dp_max_dprx_data_rate(9)

that's the whole friend group, no one left behind 🫶

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💀 friendly reminder bestie: when that return value is 0, the overall throughput cap is not indicated separately by the device — you genuinely have to derive it from the per-slice max throughput plus the max slice count. don't just vibe and assume, iykyk 😭

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and that's the page!! 🎀 source path is ./drivers/gpu/drm/display, dated October 2026, and it's drm_dp_dsc_b...l_throughput(9) on the tin — the truncated icon name, iconic honestly 💜 bye bestie, go read some DPCD ✨