dm_test_nv_...lay_count_ok(9)

💅 dm_test_nv_set_display_count_ok(9) — Kernel API Manual, bestie ✨

okay so welcome to the group chat, this is the page for dm_test_nv_set_display_count_ok and yes the manual name is a whole mood — it's a Kernel API Manual page, section 9, and the title got truncated to dm_test_nv_...lay_count_ok(9) because apparently even manpage headers have a character limit 💀 but we move.

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🌸 NAME 🌸

dm_test_nv_set_display_count_ok — Test successful display count set 🎯

like, literally, that's the whole job. it tests that setting the display count actually works. iconic behaviour ngl.

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✨ SYNOPSIS ✨

void dm_test_nv_set_display_count_ok (struct kunit *test );

that's it. that's the whole signature. one function, one argument, returns nothing (void), periodt 🫶

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🎀 ARGUMENTS 🎀

• test — KUnit test context 💖 — it's the little test-world the whole thing lives inside, and you just hand it over, no questions asked.

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🦋 DESCRIPTION 🦋

so here's the tea: this one verifies that pp_nv_set_display_count returns PP_SMU_RESULT_OK on success. that's it!! that's the entire plot. if the set goes through, the result comes back PP_SMU_RESULT_OK, and this test is literally just standing there like "yep, that's correct, slay" 👑

no cap, that's the whole description. short and sweet. main character energy in four words. 🌈

a reminder that this is a test — it verifies, it doesn't do the setting itself. don't come for me, i'm just reading the page fr fr 💀

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🔥 SEE ALSO 🔥

Kernel file 💜

./drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c

and now the whole extended friend group, all in their (9) era 💅 — every single one, no skipping, i'm not that kind of girl:

• struct stub_dpm_context(9), setup_stub_dpm(9),
• dm_test_default_clock_levels_display(9),
• dm_test_default_clock_levels_engine(9),
• dm_test_default_clock_levels_memory(9),
• dm_test_default_clock_levels_unknown(9),
• dm_test_dc_to_pp_clock_type_display(9),
• dm_test_dc_to_pp_clock_type_engine(9),
• dm_test_dc_to_pp_clock_type_memory(9),
• dm_test_dc_to_pp_clock_type_dcefclk(9),
• dm_test_dc_to_pp_clock_type_dcfclk(9),
• dm_test_dc_to_pp_clock_type_pixelclk(9),
• dm_test_dc_to_pp_clock_type_fclk(9),
• dm_test_dc_to_pp_clock_type_phyclk(9),
• dm_test_dc_to_pp_clock_type_dppclk(9),
• dm_test_dc_to_pp_clock_type_invalid(9),
• dm_test_pp_to_dc_clock_levels_within_limit(9),
• dm_test_pp_to_dc_clock_levels_caps_at_max(9),
• dm_test_pp_to_dc_clock_levels_latency_within_limit(9),
• dm_test_pp_to_dc_clock_levels_latency_caps_at_max(9),
• dm_test_pp_to_dc_clock_levels_voltage_within_limit(9),
• dm_test_pp_to_dc_clock_levels_voltage_caps_at_max(9),
• dm_test_get_funcs_rv(9), dm_test_get_funcs_rv_101(9),
• dm_test_get_funcs_nv(9), dm_test_get_funcs_rn(9),
• dm_test_get_funcs_unsupported(9),
• dm_test_apply_display_requirements_dpm_disabled(9),
• dm_test_apply_clock_for_voltage_invalid_type(9),
• dm_test_build_pm_display_cfg_scalar_fields(9),
• dm_test_build_pm_display_cfg_per_display(9),
• dm_test_build_wm_clock_ranges_dmif(9),
• dm_test_build_wm_clock_ranges_mcif(9),
• dm_test_cap_clock_levels_engine_caps(9),
• dm_test_cap_clock_levels_engine_first_exceeds(9),
• dm_test_cap_clock_levels_memory_caps(9),
• dm_test_cap_clock_levels_within_limit(9),
• dm_test_cap_clock_levels_other_type(9), dm_test_nv_clock_id_dispclk(9),
• dm_test_nv_clock_id_phyclk(9), dm_test_nv_clock_id_pixelclk(9),
• dm_test_nv_clock_id_invalid(9),
• dm_test_apply_display_requirements_dpm_enabled(9),
• dm_test_get_clock_levels_by_type_dpm_error(9),
• dm_test_get_clock_levels_by_type_success(9),
• dm_test_get_clock_levels_by_type_validation_fallback(9),
• dm_test_get_clock_levels_with_latency_success(9),
• dm_test_get_clock_levels_with_latency_failure(9),
• dm_test_get_clock_levels_with_voltage_success(9),
• dm_test_get_clock_levels_with_voltage_failure(9),
• dm_test_notify_wm_clock_changes_polaris(9),
• dm_test_notify_wm_clock_changes_non_polaris(9),
• dm_test_apply_clock_for_voltage_success(9),
• dm_test_apply_clock_for_voltage_eopnotsupp(9),
• dm_test_apply_clock_for_voltage_fail(9),
• dm_test_nv_set_display_count_unsupported(9),
• dm_test_nv_set_display_count_fail(9),
• dm_test_nv_set_voltage_by_freq_ok(9),
• dm_test_nv_set_voltage_by_freq_invalid_id(9),
• dm_test_nv_pstate_handshake_ok(9), dm_test_nv_pstate_handshake_fail(9),
• dm_test_rn_get_dpm_clock_table_ok(9),
• dm_test_rn_get_dpm_clock_table_unsupported(9),
• dm_test_rn_get_dpm_clock_table_fail(9), dm_test_rv_set_wm_ranges(9),
• dm_test_rv_set_pme_wa_enable(9), dm_test_rv_set_active_display_count(9),
• dm_test_rv_set_min_deep_sleep_dcfclk(9),
• dm_test_rv_set_hard_min_dcefclk_by_freq(9),
• dm_test_rv_set_hard_min_fclk_by_freq(9), dm_test_nv_set_wm_ranges(9),
• dm_test_nv_set_min_deep_sleep_dcfclk_ok(9),
• dm_test_nv_set_min_deep_sleep_dcfclk_unsupported(9),
• dm_test_nv_set_min_deep_sleep_dcfclk_fail(9),
• dm_test_nv_set_hard_min_dcefclk_ok(9),
• dm_test_nv_set_hard_min_dcefclk_unsupported(9),
• dm_test_nv_set_hard_min_dcefclk_fail(9),
• dm_test_nv_set_hard_min_uclk_ok(9),
• dm_test_nv_set_hard_min_uclk_unsupported(9),
• dm_test_nv_set_hard_min_uclk_fail(9),
• dm_test_nv_get_max_sustainable_clocks_ok(9),
• dm_test_nv_get_max_sustainable_clocks_unsupported(9),
• dm_test_nv_get_max_sustainable_clocks_fail(9),
• dm_test_nv_get_uclk_dpm_states_ok(9),
• dm_test_nv_get_uclk_dpm_states_unsupported(9),
• dm_test_nv_get_uclk_dpm_states_fail(9),
• dm_test_smu_write_watermarks_table_default(9)

like… the way this list just keeps going. obsessed with the commitment honestly 🧚

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🌷 okay that's the whole page, bestie! source path got trimmed to ./drivers/gpu/drm/amd/display/... and this cutie was dated October 2026 — so yeah, born in the future, still serving dm_test_nv_...lay_count_ok(9) realness. 💖 go touch some grass (or a GPU driver test suite, same vibe) 🦋✨