dm_test_cap_..._engine_caps(9)

💅 dm_test_cap_..._engine_caps(9) — like, the Kernel API Manual, but make it make sense 🎀

okay bestie, so this is a page from the Kernel API Manual and it's about a KUnit test in the DRM/AMD display test suite. the full name is a whole mouthful: dm_test_cap_clock_levels_engine_caps. no cap, it's giving "my function name is a paragraph" energy but we move 💖

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✨ NAME ✨

dm_test_cap_clock_levels_engine_caps — it tests the capping of engine clock levels. that's it, that's the whole vibe 🦋

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🌸 SYNOPSIS 🌸

void dm_test_cap_clock_levels_engine_caps (struct kunit *test );

literally one function, zero drama, takes one thing and returns nothing 💅

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🎀 ARGUMENTS 🎀

• test — the KUnit test context. it's the little backpack the test carries around so it knows where it is and what it's doing 🫶

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⭐ DESCRIPTION ⭐

okay so here's what this test is actually checking, and it's lowkey cute:

it verifies that for engine clocks, num_levels gets reduced down to the index of the first level whose frequency exceeds the engine validation clock. like, once we find the first level that's too much, we cap it right there. iconic behavior honestly 🔥

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🦋 SEE ALSO 🦋

and here's the whole group chat — every single sibling test and struct that's in the same orbit. yes, all of them. we're not skipping anyone, everyone gets an invite 💌

the kernel file itself: ./drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c

the structs and setups: struct stub_dpm_context(9), setup_stub_dpm(9)

the default clock level squad: dm_test_default_clock_levels_display(9), dm_test_default_clock_levels_engine(9), dm_test_default_clock_levels_memory(9), dm_test_default_clock_levels_unknown(9)

the clock type converters, aka the translation girlies: dm_test_dc_to_pp_clock_type_display(9), dm_test_dc_to_pp_clock_type_engine(9), dm_test_dc_to_pp_clock_type_memory(9), dm_test_dc_to_pp_clock_type_dcefclk(9), dm_test_dc_to_pp_clock_type_dcfclk(9), dm_test_dc_to_pp_clock_type_pixelclk(9), dm_test_dc_to_pp_clock_type_fclk(9), dm_test_dc_to_pp_clock_type_phyclk(9), dm_test_dc_to_pp_clock_type_dppclk(9), dm_test_dc_to_pp_clock_type_invalid(9)

pp→dc clock levels, capping and latency and voltage edition: dm_test_pp_to_dc_clock_levels_within_limit(9), dm_test_pp_to_dc_clock_levels_caps_at_max(9), dm_test_pp_to_dc_clock_levels_latency_within_limit(9), dm_test_pp_to_dc_clock_levels_latency_caps_at_max(9), dm_test_pp_to_dc_clock_levels_voltage_within_limit(9), dm_test_pp_to_dc_clock_levels_voltage_caps_at_max(9)

the funcs-getting crew: dm_test_get_funcs_rv(9), dm_test_get_funcs_rv_101(9), dm_test_get_funcs_nv(9), dm_test_get_funcs_rn(9), dm_test_get_funcs_unsupported(9)

display requirements + voltage: dm_test_apply_display_requirements_dpm_disabled(9), dm_test_apply_clock_for_voltage_invalid_type(9)

build the config, build the ranges: dm_test_build_pm_display_cfg_scalar_fields(9), dm_test_build_pm_display_cfg_per_display(9), dm_test_build_wm_clock_ranges_dmif(9), dm_test_build_wm_clock_ranges_mcif(9)

clock level capping, the rest of the family: dm_test_cap_clock_levels_engine_first_exceeds(9), dm_test_cap_clock_levels_memory_caps(9), dm_test_cap_clock_levels_within_limit(9), dm_test_cap_clock_levels_other_type(9)

nv clock ids: dm_test_nv_clock_id_dispclk(9), dm_test_nv_clock_id_phyclk(9), dm_test_nv_clock_id_pixelclk(9), dm_test_nv_clock_id_invalid(9)

more display requirements, but enabled this time: dm_test_apply_display_requirements_dpm_enabled(9)

get clock levels by type: dm_test_get_clock_levels_by_type_dpm_error(9), dm_test_get_clock_levels_by_type_success(9), dm_test_get_clock_levels_by_type_validation_fallback(9)

get clock levels with latency / with voltage: dm_test_get_clock_levels_with_latency_success(9), dm_test_get_clock_levels_with_latency_failure(9), dm_test_get_clock_levels_with_voltage_success(9), dm_test_get_clock_levels_with_voltage_failure(9)

notify wm clock changes: dm_test_notify_wm_clock_changes_polaris(9), dm_test_notify_wm_clock_changes_non_polaris(9)

apply clock for voltage, all three moods: dm_test_apply_clock_for_voltage_success(9), dm_test_apply_clock_for_voltage_eopnotsupp(9), dm_test_apply_clock_for_voltage_fail(9)

nv set display count: dm_test_nv_set_display_count_ok(9), dm_test_nv_set_display_count_unsupported(9), dm_test_nv_set_display_count_fail(9)

nv set voltage by freq: dm_test_nv_set_voltage_by_freq_ok(9), dm_test_nv_set_voltage_by_freq_invalid_id(9)

nv pstate handshake: dm_test_nv_pstate_handshake_ok(9), dm_test_nv_pstate_handshake_fail(9)

rn get dpm clock table: dm_test_rn_get_dpm_clock_table_ok(9), dm_test_rn_get_dpm_clock_table_unsupported(9), dm_test_rn_get_dpm_clock_table_fail(9)

rv stuff: dm_test_rv_set_wm_ranges(9), dm_test_rv_set_pme_wa_enable(9), dm_test_rv_set_active_display_count(9), dm_test_rv_set_min_deep_sleep_dcfclk(9), dm_test_rv_set_hard_min_dcefclk_by_freq(9), dm_test_rv_set_hard_min_fclk_by_freq(9)

nv wm ranges: dm_test_nv_set_wm_ranges(9)

nv min deep sleep dcfclk: dm_test_nv_set_min_deep_sleep_dcfclk_ok(9), dm_test_nv_set_min_deep_sleep_dcfclk_unsupported(9), dm_test_nv_set_min_deep_sleep_dcfclk_fail(9)

nv hard min dcefclk: dm_test_nv_set_hard_min_dcefclk_ok(9), dm_test_nv_set_hard_min_dcefclk_unsupported(9), dm_test_nv_set_hard_min_dcefclk_fail(9)

nv hard min uclk: dm_test_nv_set_hard_min_uclk_ok(9), dm_test_nv_set_hard_min_uclk_unsupported(9), dm_test_nv_set_hard_min_uclk_fail(9)

nv max sustainable clocks: dm_test_nv_get_max_sustainable_clocks_ok(9), dm_test_nv_get_max_sustainable_clocks_unsupported(9), dm_test_nv_get_max_sustainable_clocks_fail(9)

nv uclk dpm states: dm_test_nv_get_uclk_dpm_states_ok(9), dm_test_nv_get_uclk_dpm_states_unsupported(9), dm_test_nv_get_uclk_dpm_states_fail(9)

and the last one, standing on its own: dm_test_smu_write_watermarks_table_default(9)

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fr fr that's the whole list — nothing dropped, nothing merged, we keep every single reference because that's what besties do 💜

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okay that's the page!! source path is ./drivers/gpu/drm/amd/display/... and it's dated October 2026, so like, future girlie behavior honestly 🌈✨ bye bestie, go cap those engine clocks 💅👑