dm_test_nv_clock_id_invalid(9)

✨ dm_test_nv_clock_id_invalid 💅

okay so bestie, welcome to the Kernel API Manual — today we're looking at dm_test_nv_clock_id_invalid(9) and honestly? it's a little icon of defensive programming 🎀

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🌸 NAME 🌸

dm_test_nv_clock_id_invalid — literally just here to test that an unknown id gets rejected 🙅‍♀️

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🦋 SYNOPSIS 🦋

void dm_test_nv_clock_id_invalid (struct kunit *test );

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💖 ARGUMENTS 💖

• test — the KUnit test context, aka the group chat where this test tells everyone how it went 🫶

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✨ DESCRIPTION ✨

so the whole vibe here is verification, no cap: an unknown clock id needs to return false, and it needs to leave the output clock_type untouched. that's it, that's the assignment 💅

and why do we care? because it's guarding against the previously uninitialized path — like, bestie, that path used to be out here with no initialization and we are not going back 😭👑

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🌈 SEE ALSO 🌈

📁 Kernel file

./drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c

🧚 the whole friend group (all of these are real, i checked, every single one)

• struct stub_dpm_context(9), setup_stub_dpm(9)
• dm_test_default_clock_levels_display(9), dm_test_default_clock_levels_engine(9), dm_test_default_clock_levels_memory(9), dm_test_default_clock_levels_unknown(9)
• dm_test_dc_to_pp_clock_type_display(9), dm_test_dc_to_pp_clock_type_engine(9), dm_test_dc_to_pp_clock_type_memory(9), dm_test_dc_to_pp_clock_type_dcefclk(9), dm_test_dc_to_pp_clock_type_dcfclk(9), dm_test_dc_to_pp_clock_type_pixelclk(9), dm_test_dc_to_pp_clock_type_fclk(9), dm_test_dc_to_pp_clock_type_phyclk(9), dm_test_dc_to_pp_clock_type_dppclk(9), dm_test_dc_to_pp_clock_type_invalid(9)
• dm_test_pp_to_dc_clock_levels_within_limit(9), dm_test_pp_to_dc_clock_levels_caps_at_max(9), dm_test_pp_to_dc_clock_levels_latency_within_limit(9), dm_test_pp_to_dc_clock_levels_latency_caps_at_max(9), dm_test_pp_to_dc_clock_levels_voltage_within_limit(9), dm_test_pp_to_dc_clock_levels_voltage_caps_at_max(9)
• dm_test_get_funcs_rv(9), dm_test_get_funcs_rv_101(9), dm_test_get_funcs_nv(9), dm_test_get_funcs_rn(9), dm_test_get_funcs_unsupported(9)
• dm_test_apply_display_requirements_dpm_disabled(9), dm_test_apply_clock_for_voltage_invalid_type(9)
• dm_test_build_pm_display_cfg_scalar_fields(9), dm_test_build_pm_display_cfg_per_display(9)
• dm_test_build_wm_clock_ranges_dmif(9), dm_test_build_wm_clock_ranges_mcif(9)
• dm_test_cap_clock_levels_engine_caps(9), dm_test_cap_clock_levels_engine_first_exceeds(9), dm_test_cap_clock_levels_memory_caps(9), dm_test_cap_clock_levels_within_limit(9), dm_test_cap_clock_levels_other_type(9)
• dm_test_nv_clock_id_dispclk(9), dm_test_nv_clock_id_phyclk(9), dm_test_nv_clock_id_pixelclk(9)
• dm_test_apply_display_requirements_dpm_enabled(9)
• dm_test_get_clock_levels_by_type_dpm_error(9), dm_test_get_clock_levels_by_type_success(9), dm_test_get_clock_levels_by_type_validation_fallback(9)
• dm_test_get_clock_levels_with_latency_success(9), dm_test_get_clock_levels_with_latency_failure(9)
• dm_test_get_clock_levels_with_voltage_success(9), dm_test_get_clock_levels_with_voltage_failure(9)
• dm_test_notify_wm_clock_changes_polaris(9), dm_test_notify_wm_clock_changes_non_polaris(9)
• dm_test_apply_clock_for_voltage_success(9), dm_test_apply_clock_for_voltage_eopnotsupp(9), dm_test_apply_clock_for_voltage_fail(9)
• dm_test_nv_set_display_count_ok(9), dm_test_nv_set_display_count_unsupported(9), dm_test_nv_set_display_count_fail(9)
• dm_test_nv_set_voltage_by_freq_ok(9), dm_test_nv_set_voltage_by_freq_invalid_id(9)
• dm_test_nv_pstate_handshake_ok(9), dm_test_nv_pstate_handshake_fail(9)
• dm_test_rn_get_dpm_clock_table_ok(9), dm_test_rn_get_dpm_clock_table_unsupported(9), dm_test_rn_get_dpm_clock_table_fail(9)
• dm_test_rv_set_wm_ranges(9), dm_test_rv_set_pme_wa_enable(9), dm_test_rv_set_active_display_count(9), dm_test_rv_set_min_deep_sleep_dcfclk(9), dm_test_rv_set_hard_min_dcefclk_by_freq(9), dm_test_rv_set_hard_min_fclk_by_freq(9)
• dm_test_nv_set_wm_ranges(9)
• dm_test_nv_set_min_deep_sleep_dcfclk_ok(9), dm_test_nv_set_min_deep_sleep_dcfclk_unsupported(9), dm_test_nv_set_min_deep_sleep_dcfclk_fail(9)
• dm_test_nv_set_hard_min_dcefclk_ok(9), dm_test_nv_set_hard_min_dcefclk_unsupported(9), dm_test_nv_set_hard_min_dcefclk_fail(9)
• dm_test_nv_set_hard_min_uclk_ok(9), dm_test_nv_set_hard_min_uclk_unsupported(9), dm_test_nv_set_hard_min_uclk_fail(9)
• dm_test_nv_get_max_sustainable_clocks_ok(9), dm_test_nv_get_max_sustainable_clocks_unsupported(9), dm_test_nv_get_max_sustainable_clocks_fail(9)
• dm_test_nv_get_uclk_dpm_states_ok(9), dm_test_nv_get_uclk_dpm_states_unsupported(9), dm_test_nv_get_uclk_dpm_states_fail(9)
• dm_test_smu_write_watermarks_table_default(9)

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okay that's the whole thing, go read the source file if you want the lore 🍓

source path: ./drivers/gpu/drm/amd/display/... · version: the manual one · date: October 2026 — mwah, love u, bye bestie 💜🎀✨👑