dm_test_nv_g...le_clocks_ok(9)
β¨ dm_test_nv_g...le_clocks_ok(9) β¨
okay so bestie, welcome to the Kernel API Manual π
this whole page is about dm_test_nv_get_max_sustainable_clocks_ok(9) and honestly it's a little guy with a big job. buckle up π
πΈ NAME πΈ
dm_test_nv_get_max_sustainable_clocks_ok β the test that's like "did the query actually work tho?" πβ¨
π¦ SYNOPSIS π¦
void dm_test_nv_get_max_sustainable_clocks_ok (struct kunit *test );
that's it. that's the whole signature. slay π
π ARGUMENTS π
testβ the KUnit test context π§ this is the little bubble of state the whole test runs inside, so it knows who it is and where it lives.
π DESCRIPTION π
okay so the entire vibe here: this test verifies that pp_nv_get_maximum_sustainable_clocks returns PP_SMU_RESULT_OK. that's the whole assignment π like, no cap, it just checks that the call came back happy. one function, one expected result, one very good little pass/fail moment. the way that the whole test exists just to confirm PP_SMU_RESULT_OK came backβ¦ obsessed π«Ά
π SEE ALSO π
right so before we get into the list β there's a kernel file involved, and yes you should go look at it, it's literally where the party's at π
./drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c
and here's the full bestie roll call, no one gets left behind, fr fr π
struct stub_dpm_context(9)setup_stub_dpm(9)dm_test_default_clock_levels_display(9)dm_test_default_clock_levels_engine(9)dm_test_default_clock_levels_memory(9)dm_test_default_clock_levels_unknown(9)dm_test_dc_to_pp_clock_type_display(9)dm_test_dc_to_pp_clock_type_engine(9)dm_test_dc_to_pp_clock_type_memory(9)dm_test_dc_to_pp_clock_type_dcefclk(9)dm_test_dc_to_pp_clock_type_dcfclk(9)dm_test_dc_to_pp_clock_type_pixelclk(9)dm_test_dc_to_pp_clock_type_fclk(9)dm_test_dc_to_pp_clock_type_phyclk(9)dm_test_dc_to_pp_clock_type_dppclk(9)dm_test_dc_to_pp_clock_type_invalid(9)dm_test_pp_to_dc_clock_levels_within_limit(9)dm_test_pp_to_dc_clock_levels_caps_at_max(9)dm_test_pp_to_dc_clock_levels_latency_within_limit(9)dm_test_pp_to_dc_clock_levels_latency_caps_at_max(9)dm_test_pp_to_dc_clock_levels_voltage_within_limit(9)dm_test_pp_to_dc_clock_levels_voltage_caps_at_max(9)dm_test_get_funcs_rv(9)dm_test_get_funcs_rv_101(9)dm_test_get_funcs_nv(9)dm_test_get_funcs_rn(9)dm_test_get_funcs_unsupported(9)dm_test_apply_display_requirements_dpm_disabled(9)dm_test_apply_clock_for_voltage_invalid_type(9)dm_test_build_pm_display_cfg_scalar_fields(9)dm_test_build_pm_display_cfg_per_display(9)dm_test_build_wm_clock_ranges_dmif(9)dm_test_build_wm_clock_ranges_mcif(9)dm_test_cap_clock_levels_engine_caps(9)dm_test_cap_clock_levels_engine_first_exceeds(9)dm_test_cap_clock_levels_memory_caps(9)dm_test_cap_clock_levels_within_limit(9)dm_test_cap_clock_levels_other_type(9)dm_test_nv_clock_id_dispclk(9)dm_test_nv_clock_id_phyclk(9)dm_test_nv_clock_id_pixelclk(9)dm_test_nv_clock_id_invalid(9)dm_test_apply_display_requirements_dpm_enabled(9)dm_test_get_clock_levels_by_type_dpm_error(9)dm_test_get_clock_levels_by_type_success(9)dm_test_get_clock_levels_by_type_validation_fallback(9)dm_test_get_clock_levels_with_latency_success(9)dm_test_get_clock_levels_with_latency_failure(9)dm_test_get_clock_levels_with_voltage_success(9)dm_test_get_clock_levels_with_voltage_failure(9)dm_test_notify_wm_clock_changes_polaris(9)dm_test_notify_wm_clock_changes_non_polaris(9)dm_test_apply_clock_for_voltage_success(9)dm_test_apply_clock_for_voltage_eopnotsupp(9)dm_test_apply_clock_for_voltage_fail(9)dm_test_nv_set_display_count_ok(9)dm_test_nv_set_display_count_unsupported(9)dm_test_nv_set_display_count_fail(9)dm_test_nv_set_voltage_by_freq_ok(9)dm_test_nv_set_voltage_by_freq_invalid_id(9)dm_test_nv_pstate_handshake_ok(9)dm_test_nv_pstate_handshake_fail(9)dm_test_rn_get_dpm_clock_table_ok(9)dm_test_rn_get_dpm_clock_table_unsupported(9)dm_test_rn_get_dpm_clock_table_fail(9)dm_test_rv_set_wm_ranges(9)dm_test_rv_set_pme_wa_enable(9)dm_test_rv_set_active_display_count(9)dm_test_rv_set_min_deep_sleep_dcfclk(9)dm_test_rv_set_hard_min_dcefclk_by_freq(9)dm_test_rv_set_hard_min_fclk_by_freq(9)dm_test_nv_set_wm_ranges(9)dm_test_nv_set_min_deep_sleep_dcfclk_ok(9)dm_test_nv_set_min_deep_sleep_dcfclk_unsupported(9)dm_test_nv_set_min_deep_sleep_dcfclk_fail(9)dm_test_nv_set_hard_min_dcefclk_ok(9)dm_test_nv_set_hard_min_dcefclk_unsupported(9)dm_test_nv_set_hard_min_dcefclk_fail(9)dm_test_nv_set_hard_min_uclk_ok(9)dm_test_nv_set_hard_min_uclk_unsupported(9)dm_test_nv_set_hard_min_uclk_fail(9)dm_test_nv_get_max_sustainable_clocks_unsupported(9)dm_test_nv_get_max_sustainable_clocks_fail(9)dm_test_nv_get_uclk_dpm_states_ok(9)dm_test_nv_get_uclk_dpm_states_unsupported(9)dm_test_nv_get_uclk_dpm_states_fail(9)dm_test_smu_write_watermarks_table_default(9)
likeβ¦ that's the whole friend group π every single one of them, all (9), all accounted for π
ngl this page is short but it's giving main character energy β one function, one PP_SMU_RESULT_OK, zero drama π¦
and that's the tea, bestie π this came out of ./drivers/gpu/drm/amd/display/... and the version vibes are October 2026 β go forth and let PP_SMU_RESULT_OK be your roman empire π
β¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms