dm_test_cap...within_limit(9)
π dm_test_cap...within_limit(9) β the Kernel API Manual, but make it cute
okay bestie, so this page lives in the Kernel API Manual under the name dm_test_cap...within_limit(9), and honestly? It's a tiny little test function with a big personality. Let's get into it β¨
πΈ NAME
dm_test_cap_clock_levels_within_limit β the test that proves nothing gets capped when everything's already within the limit. She's a good girl, your honor π
β¨ SYNOPSIS
void dm_test_cap_clock_levels_within_limit (struct kunit *test );
That's it. One argument. No drama. Periodt.
π¦ ARGUMENTS
testβ the KUnit test context. She's the whole vibe check wrapper for this test, mwah π
π₯ DESCRIPTION
So the whole point, fr fr: this test verifies that num_levels is left unchanged when no level exceeds the validation clock. Like, everybody's behaving, nobody's over the line, so nothing gets capped β and num_levels stays exactly where it was. No cap. No changes. Just vibes πβ¨
no cap literally. that's the test. the test is "no cap". i'm obsessed π
π SEE ALSO
okay this is the part where the page goes feral and lists basically every test in the file. grab a snack bestie, we're going in π
The file itself:
- Kernel file
./drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c
Struct + setup:
struct stub_dpm_context(9)setup_stub_dpm(9)
Default clock levels:
dm_test_default_clock_levels_display(9)dm_test_default_clock_levels_engine(9)dm_test_default_clock_levels_memory(9)dm_test_default_clock_levels_unknown(9)
dc_to_pp clock types:
dm_test_dc_to_pp_clock_type_display(9)dm_test_dc_to_pp_clock_type_engine(9)dm_test_dc_to_pp_clock_type_memory(9)dm_test_dc_to_pp_clock_type_dcefclk(9)dm_test_dc_to_pp_clock_type_dcfclk(9)dm_test_dc_to_pp_clock_type_pixelclk(9)dm_test_dc_to_pp_clock_type_fclk(9)dm_test_dc_to_pp_clock_type_phyclk(9)dm_test_dc_to_pp_clock_type_dppclk(9)dm_test_dc_to_pp_clock_type_invalid(9)
pp_to_dc clock levels:
dm_test_pp_to_dc_clock_levels_within_limit(9)dm_test_pp_to_dc_clock_levels_caps_at_max(9)dm_test_pp_to_dc_clock_levels_latency_within_limit(9)dm_test_pp_to_dc_clock_levels_latency_caps_at_max(9)dm_test_pp_to_dc_clock_levels_voltage_within_limit(9)dm_test_pp_to_dc_clock_levels_voltage_caps_at_max(9)
get_funcs variants:
dm_test_get_funcs_rv(9)dm_test_get_funcs_rv_101(9)dm_test_get_funcs_nv(9)dm_test_get_funcs_rn(9)dm_test_get_funcs_unsupported(9)
apply / build helpers:
dm_test_apply_display_requirements_dpm_disabled(9)dm_test_apply_clock_for_voltage_invalid_type(9)dm_test_build_pm_display_cfg_scalar_fields(9)dm_test_build_pm_display_cfg_per_display(9)dm_test_build_wm_clock_ranges_dmif(9)dm_test_build_wm_clock_ranges_mcif(9)
cap_clock_levels tests (siblings of this one π):
dm_test_cap_clock_levels_engine_caps(9)dm_test_cap_clock_levels_engine_first_exceeds(9)dm_test_cap_clock_levels_memory_caps(9)dm_test_cap_clock_levels_other_type(9)
nv clock id:
dm_test_nv_clock_id_dispclk(9)dm_test_nv_clock_id_phyclk(9)dm_test_nv_clock_id_pixelclk(9)dm_test_nv_clock_id_invalid(9)
requirements + clock-level lookups:
dm_test_apply_display_requirements_dpm_enabled(9)dm_test_get_clock_levels_by_type_dpm_error(9)dm_test_get_clock_levels_by_type_success(9)dm_test_get_clock_levels_by_type_validation_fallback(9)dm_test_get_clock_levels_with_latency_success(9)dm_test_get_clock_levels_with_latency_failure(9)dm_test_get_clock_levels_with_voltage_success(9)dm_test_get_clock_levels_with_voltage_failure(9)
watermark notifications:
apply_clock_for_voltage trio:
dm_test_apply_clock_for_voltage_success(9)dm_test_apply_clock_for_voltage_eopnotsupp(9)dm_test_apply_clock_for_voltage_fail(9)
nv display count / voltage / handshake:
dm_test_nv_set_display_count_ok(9)dm_test_nv_set_display_count_unsupported(9)dm_test_nv_set_display_count_fail(9)dm_test_nv_set_voltage_by_freq_ok(9)dm_test_nv_set_voltage_by_freq_invalid_id(9)dm_test_nv_pstate_handshake_ok(9)dm_test_nv_pstate_handshake_fail(9)
rn dpm clock table:
dm_test_rn_get_dpm_clock_table_ok(9)dm_test_rn_get_dpm_clock_table_unsupported(9)dm_test_rn_get_dpm_clock_table_fail(9)
rv set_* crew:
dm_test_rv_set_wm_ranges(9)dm_test_rv_set_pme_wa_enable(9)dm_test_rv_set_active_display_count(9)dm_test_rv_set_min_deep_sleep_dcfclk(9)dm_test_rv_set_hard_min_dcefclk_by_freq(9)dm_test_rv_set_hard_min_fclk_by_freq(9)
nv set_* crew:
dm_test_nv_set_wm_ranges(9)dm_test_nv_set_min_deep_sleep_dcfclk_ok(9)dm_test_nv_set_min_deep_sleep_dcfclk_unsupported(9)dm_test_nv_set_min_deep_sleep_dcfclk_fail(9)dm_test_nv_set_hard_min_dcefclk_ok(9)dm_test_nv_set_hard_min_dcefclk_unsupported(9)dm_test_nv_set_hard_min_dcefclk_fail(9)dm_test_nv_set_hard_min_uclk_ok(9)dm_test_nv_set_hard_min_uclk_unsupported(9)dm_test_nv_set_hard_min_uclk_fail(9)
nv sustainable clocks + uclk dpm states:
dm_test_nv_get_max_sustainable_clocks_ok(9)dm_test_nv_get_max_sustainable_clocks_unsupported(9)dm_test_nv_get_max_sustainable_clocks_fail(9)dm_test_nv_get_uclk_dpm_states_ok(9)dm_test_nv_get_uclk_dpm_states_unsupported(9)dm_test_nv_get_uclk_dpm_states_fail(9)
and one lonely little watermarks test to close it out π«Ά:
π§ sign-off
That's the whole page, bestie! Sourced from ./drivers/gpu/drm/amd/display/... β October 2026, from the Kernel API Manual. Slay, go read your tests, ily, bye πβ¨π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms