dm_test_get...ency_success(9)
β¨ dm_test_get_clock_levels_with_latency_success β a whole vibe π
okay so bestie, this is a page from the Kernel API Manual (section 9, natch) and it's about one very specific little KUnit test. she's niche, she's proud, and honestly she's kind of iconic for how much she commits to one job. let's get into it π«Ά
πΈ NAME πΈ
dm_test_get_clock_levels_with_latency_success β the test that asks "hey, does the latency clock query actually work?" and then refuses to accept anything but yes β¨
π SYNOPSIS π
void dm_test_get_clock_levels_with_latency_success (struct kunit *test
);
literally one argument, no drama, no options, no flags β just vibes and a test context π¦
π ARGUMENTS π
testβ the KUnit test context. it's the little passport this test carries around so KUnit knows who it is and where to file the results. main character energy, honestly π
π§ DESCRIPTION π§
okay so here's the whole thing: this test verifies that dm_pp_get_clock_levels_by_type_with_latency returns true π and that it actually copies the clock/latency data from the DPM backend. that's it. that's the whole test. it's giving "trust but verify" but make it a unit test.
so like β data goes in from the DPM backend, true comes back out, and if either of those things doesn't happen, this test is going to have something to say about it. no cap. π₯
β SEE ALSO β
π¦ the file itself
Kernel file:
./drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c
π the whole friend group (yes, all of them)
struct stub_dpm_context(9)setup_stub_dpm(9)dm_test_default_clock_levels_display(9)dm_test_default_clock_levels_engine(9)dm_test_default_clock_levels_memory(9)dm_test_default_clock_levels_unknown(9)dm_test_dc_to_pp_clock_type_display(9)dm_test_dc_to_pp_clock_type_engine(9)dm_test_dc_to_pp_clock_type_memory(9)dm_test_dc_to_pp_clock_type_dcefclk(9)dm_test_dc_to_pp_clock_type_dcfclk(9)dm_test_dc_to_pp_clock_type_pixelclk(9)dm_test_dc_to_pp_clock_type_fclk(9)dm_test_dc_to_pp_clock_type_phyclk(9)dm_test_dc_to_pp_clock_type_dppclk(9)dm_test_dc_to_pp_clock_type_invalid(9)dm_test_pp_to_dc_clock_levels_within_limit(9)dm_test_pp_to_dc_clock_levels_caps_at_max(9)dm_test_pp_to_dc_clock_levels_latency_within_limit(9)dm_test_pp_to_dc_clock_levels_latency_caps_at_max(9)dm_test_pp_to_dc_clock_levels_voltage_within_limit(9)dm_test_pp_to_dc_clock_levels_voltage_caps_at_max(9)dm_test_get_funcs_rv(9)dm_test_get_funcs_rv_101(9)dm_test_get_funcs_nv(9)dm_test_get_funcs_rn(9)dm_test_get_funcs_unsupported(9)dm_test_apply_display_requirements_dpm_disabled(9)dm_test_apply_clock_for_voltage_invalid_type(9)dm_test_build_pm_display_cfg_scalar_fields(9)dm_test_build_pm_display_cfg_per_display(9)dm_test_build_wm_clock_ranges_dmif(9)dm_test_build_wm_clock_ranges_mcif(9)dm_test_cap_clock_levels_engine_caps(9)dm_test_cap_clock_levels_engine_first_exceeds(9)dm_test_cap_clock_levels_memory_caps(9)dm_test_cap_clock_levels_within_limit(9)dm_test_cap_clock_levels_other_type(9)dm_test_nv_clock_id_dispclk(9)dm_test_nv_clock_id_phyclk(9)dm_test_nv_clock_id_pixelclk(9)dm_test_nv_clock_id_invalid(9)dm_test_apply_display_requirements_dpm_enabled(9)dm_test_get_clock_levels_by_type_dpm_error(9)dm_test_get_clock_levels_by_type_success(9)dm_test_get_clock_levels_by_type_validation_fallback(9)dm_test_get_clock_levels_with_latency_failure(9)dm_test_get_clock_levels_with_voltage_success(9)dm_test_get_clock_levels_with_voltage_failure(9)dm_test_notify_wm_clock_changes_polaris(9)dm_test_notify_wm_clock_changes_non_polaris(9)dm_test_apply_clock_for_voltage_success(9)dm_test_apply_clock_for_voltage_eopnotsupp(9)dm_test_apply_clock_for_voltage_fail(9)dm_test_nv_set_display_count_ok(9)dm_test_nv_set_display_count_unsupported(9)dm_test_nv_set_display_count_fail(9)dm_test_nv_set_voltage_by_freq_ok(9)dm_test_nv_set_voltage_by_freq_invalid_id(9)dm_test_nv_pstate_handshake_ok(9)dm_test_nv_pstate_handshake_fail(9)dm_test_rn_get_dpm_clock_table_ok(9)dm_test_rn_get_dpm_clock_table_unsupported(9)dm_test_rn_get_dpm_clock_table_fail(9)dm_test_rv_set_wm_ranges(9)dm_test_rv_set_pme_wa_enable(9)dm_test_rv_set_active_display_count(9)dm_test_rv_set_min_deep_sleep_dcfclk(9)dm_test_rv_set_hard_min_dcefclk_by_freq(9)dm_test_rv_set_hard_min_fclk_by_freq(9)dm_test_nv_set_wm_ranges(9)dm_test_nv_set_min_deep_sleep_dcfclk_ok(9)dm_test_nv_set_min_deep_sleep_dcfclk_unsupported(9)dm_test_nv_set_min_deep_sleep_dcfclk_fail(9)dm_test_nv_set_hard_min_dcefclk_ok(9)dm_test_nv_set_hard_min_dcefclk_unsupported(9)dm_test_nv_set_hard_min_dcefclk_fail(9)dm_test_nv_set_hard_min_uclk_ok(9)dm_test_nv_set_hard_min_uclk_unsupported(9)dm_test_nv_set_hard_min_uclk_fail(9)dm_test_nv_get_max_sustainable_clocks_ok(9)dm_test_nv_get_max_sustainable_clocks_unsupported(9)dm_test_nv_get_max_sustainable_clocks_fail(9)dm_test_nv_get_uclk_dpm_states_ok(9)dm_test_nv_get_uclk_dpm_states_unsupported(9)dm_test_nv_get_uclk_dpm_states_fail(9)dm_test_smu_write_watermarks_table_default(9)
like I said. the whole friend group. every single one of them showed up to the group chat ππ
ngl bestie, there are no OPTIONS, no exit statuses, no env vars, no signals on this page β she's a one-function wonder and she knows it. don't go looking for plot twists that aren't there π
mwah π that's the page! it lives over at ./drivers/gpu/drm/amd/display/... and the whole thing is stamped October 2026 β so mark your calendar, screenshot it, frame it, whatever, because this test is slaying in the Kernel API Manual and we're all just living in her timeline β¨ππ
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms