dm_test_pp_t...within_limit(9)
π dm_test_pp_t...within_limit(9) β like, the Kernel API Manual, but make it make sense β¨
okay so bestie, welcome to section 9 of the Kernel API Manual β yes, the fancy kernel-doc one, not yourεΈΈθ§ user-commands man page. this little diva right here is dm_test_pp_to_dc_clock_levels_within_limit, and no, the title up top got abbreviated to dm_test_pp_t...within_limit(9) because apparently even man pages get a nickname. iconic behavior honestly π
πΈ NAME πΈ
dm_test_pp_to_dc_clock_levels_within_limit β the test that checks a normal copy stays, y'know, within limit. that's it. that's the whole vibe. π
β¨ SYNOPSIS β¨
void dm_test_pp_to_dc_clock_levels_within_limit (struct kunit *test );like, it returns void and takes exactly one thing. no notes. π«Ά
π¦ ARGUMENTS π¦
testβ your KUnit test context π that's the whole argument list, she's low-maintenance.
π DESCRIPTION π
okay so here's the tea, bestie: this test verifies that pp_to_dc_clock_levels correctly copies clock values π₯ when the count is within DM_PP_MAX_CLOCK_LEVELS. that's the one job. copy the clocks, stay under the max, slay. no cap. β¨
π SEE ALSO π
π The kernel file, aka where she lives
./drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.cπ§ the struct & setup besties
struct stub_dpm_context(9)setup_stub_dpm(9)
π the clock-levels default squad
dm_test_default_clock_levels_display(9)dm_test_default_clock_levels_engine(9)dm_test_default_clock_levels_memory(9)dm_test_default_clock_levels_unknown(9)
π the dc_to_pp_clock_type girlies (there are SO many, she's thorough)
dm_test_dc_to_pp_clock_type_display(9)dm_test_dc_to_pp_clock_type_engine(9)dm_test_dc_to_pp_clock_type_memory(9)dm_test_dc_to_pp_clock_type_dcefclk(9)dm_test_dc_to_pp_clock_type_dcfclk(9)dm_test_dc_to_pp_clock_type_pixelclk(9)dm_test_dc_to_pp_clock_type_fclk(9)dm_test_dc_to_pp_clock_type_phyclk(9)dm_test_dc_to_pp_clock_type_dppclk(9)dm_test_dc_to_pp_clock_type_invalid(9)
β the pp_to_dc_clock_levels family (our main character's siblings)
dm_test_pp_to_dc_clock_levels_caps_at_max(9)dm_test_pp_to_dc_clock_levels_latency_within_limit(9)dm_test_pp_to_dc_clock_levels_latency_caps_at_max(9)dm_test_pp_to_dc_clock_levels_voltage_within_limit(9)dm_test_pp_to_dc_clock_levels_voltage_caps_at_max(9)
π₯ the get_funcs crew
dm_test_get_funcs_rv(9)dm_test_get_funcs_rv_101(9)dm_test_get_funcs_nv(9)dm_test_get_funcs_rn(9)dm_test_get_funcs_unsupported(9)
π display requirements / clock-for-voltage tests
dm_test_apply_display_requirements_dpm_disabled(9)dm_test_apply_clock_for_voltage_invalid_type(9)dm_test_build_pm_display_cfg_scalar_fields(9)dm_test_build_pm_display_cfg_per_display(9)dm_test_build_wm_clock_ranges_dmif(9)dm_test_build_wm_clock_ranges_mcif(9)
𧡠the cap_clock_levels set
dm_test_cap_clock_levels_engine_caps(9)dm_test_cap_clock_levels_engine_first_exceeds(9)dm_test_cap_clock_levels_memory_caps(9)dm_test_cap_clock_levels_within_limit(9)dm_test_cap_clock_levels_other_type(9)
πΈ the nv_clock_id crew
dm_test_nv_clock_id_dispclk(9)dm_test_nv_clock_id_phyclk(9)dm_test_nv_clock_id_pixelclk(9)dm_test_nv_clock_id_invalid(9)
π«Ά apply-display-requirements & clock-levels-by-type crew
dm_test_apply_display_requirements_dpm_enabled(9)dm_test_get_clock_levels_by_type_dpm_error(9)dm_test_get_clock_levels_by_type_success(9)dm_test_get_clock_levels_by_type_validation_fallback(9)dm_test_get_clock_levels_with_latency_success(9)dm_test_get_clock_levels_with_latency_failure(9)dm_test_get_clock_levels_with_voltage_success(9)dm_test_get_clock_levels_with_voltage_failure(9)dm_test_notify_wm_clock_changes_polaris(9)dm_test_notify_wm_clock_changes_non_polaris(9)dm_test_apply_clock_for_voltage_success(9)dm_test_apply_clock_for_voltage_eopnotsupp(9)dm_test_apply_clock_for_voltage_fail(9)
π the nv_ set-display-count trio
dm_test_nv_set_display_count_ok(9)dm_test_nv_set_display_count_unsupported(9)dm_test_nv_set_display_count_fail(9)
π« the nv_ voltage / pstate / dpm-table besties
dm_test_nv_set_voltage_by_freq_ok(9)dm_test_nv_set_voltage_by_freq_invalid_id(9)dm_test_nv_pstate_handshake_ok(9)dm_test_nv_pstate_handshake_fail(9)dm_test_rn_get_dpm_clock_table_ok(9)dm_test_rn_get_dpm_clock_table_unsupported(9)dm_test_rn_get_dpm_clock_table_fail(9)
β the rv_ setting squad
dm_test_rv_set_wm_ranges(9)dm_test_rv_set_pme_wa_enable(9)dm_test_rv_set_active_display_count(9)dm_test_rv_set_min_deep_sleep_dcfclk(9)dm_test_rv_set_hard_min_dcefclk_by_freq(9)dm_test_rv_set_hard_min_fclk_by_freq(9)
π the nv_ setting squad (she has a LOT of nv_ tests fr fr)
dm_test_nv_set_wm_ranges(9)dm_test_nv_set_min_deep_sleep_dcfclk_ok(9)dm_test_nv_set_min_deep_sleep_dcfclk_unsupported(9)dm_test_nv_set_min_deep_sleep_dcfclk_fail(9)dm_test_nv_set_hard_min_dcefclk_ok(9)dm_test_nv_set_hard_min_dcefclk_unsupported(9)dm_test_nv_set_hard_min_dcefclk_fail(9)dm_test_nv_set_hard_min_uclk_ok(9)dm_test_nv_set_hard_min_uclk_unsupported(9)dm_test_nv_set_hard_min_uclk_fail(9)dm_test_nv_get_max_sustainable_clocks_ok(9)dm_test_nv_get_max_sustainable_clocks_unsupported(9)dm_test_nv_get_max_sustainable_clocks_fail(9)dm_test_nv_get_uclk_dpm_states_ok(9)dm_test_nv_get_uclk_dpm_states_unsupported(9)dm_test_nv_get_uclk_dpm_states_fail(9)
π and one more for the road
π real talk bestie: this SEE ALSO list is genuinely enormous and i am NOT skipping a single one of these. every single (9) reference stays. ctrl+F is your friend, periodt. π₯
and that's the whole page, bestie! π she came from ./drivers/gpu/drm/amd/display/... and she's dated October 2026 β don't lose her, she's iconic. byeee πβ¨π¦π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms