dm_test_get_funcs_nv(9)
π dm_test_get_funcs_nv(9) β from the Kernel API Manual, bestie
okay so. this page is literally a kernel API manual entry, section 9, and it's about dm_test_get_funcs_nv. yes the name is a mouthful, no we are not abbreviating it. let's go β¨
β¨ NAME β¨
dm_test_get_funcs_nv β Test Navi PP SMU function table setup π
like that's the whole vibe. it's a test. about a function table. for Navi. we move.
π¦ SYNOPSIS π¦
void dm_test_get_funcs_nv (struct kunit *test );
that's it. that's the signature. copy it exactly, don't get cute with the spacing, the spacing is load-bearing (it is not, but respect it anyway π).
πΈ ARGUMENTS πΈ
testβ the KUnit test context. that's it. that's the whole argument list. one (1) parameter and she ate π
π₯ DESCRIPTION π₯
so what does this actually do. ok so basically: this test verifies that DCN 2.0 initializes the Navi SMU function table β and then it also verifies that the unsupported PME workaround callback is left unset. π
like the whole point is that it gets set up correctly and that the thing that should NOT be set stays not-set. double check, double slay. no cap, that's the entire test.
fr fr, "unsupported" here is the point, not a bug β the test is literally checking that the callback stays unset. don't come for her π
π SEE ALSO π
okay this next part is long. like long long. but every single one of these is a real reference and we are not skipping a single one, because skipping is not the vibe. grab a snack bestie π
The source file:
- Kernel file
./drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_pp_smu_test.c
Structs & setup:
struct stub_dpm_context(9)setup_stub_dpm(9)
Default clock levels:
dm_test_default_clock_levels_display(9)dm_test_default_clock_levels_engine(9)dm_test_default_clock_levels_memory(9)dm_test_default_clock_levels_unknown(9)
dc β pp clock type conversions:
dm_test_dc_to_pp_clock_type_display(9)dm_test_dc_to_pp_clock_type_engine(9)dm_test_dc_to_pp_clock_type_memory(9)dm_test_dc_to_pp_clock_type_dcefclk(9)dm_test_dc_to_pp_clock_type_dcfclk(9)dm_test_dc_to_pp_clock_type_pixelclk(9)dm_test_dc_to_pp_clock_type_fclk(9)dm_test_dc_to_pp_clock_type_phyclk(9)dm_test_dc_to_pp_clock_type_dppclk(9)dm_test_dc_to_pp_clock_type_invalid(9)
pp β dc clock levels:
dm_test_pp_to_dc_clock_levels_within_limit(9)dm_test_pp_to_dc_clock_levels_caps_at_max(9)dm_test_pp_to_dc_clock_levels_latency_within_limit(9)dm_test_pp_to_dc_clock_levels_latency_caps_at_max(9)dm_test_pp_to_dc_clock_levels_voltage_within_limit(9)dm_test_pp_to_dc_clock_levels_voltage_caps_at_max(9)
the sibling get_funcs tests (our girl's family π«Ά):
dm_test_get_funcs_rv(9)dm_test_get_funcs_rv_101(9)dm_test_get_funcs_rn(9)dm_test_get_funcs_unsupported(9)
display requirements & volt/clock plumbing:
dm_test_apply_display_requirements_dpm_disabled(9)dm_test_apply_clock_for_voltage_invalid_type(9)dm_test_build_pm_display_cfg_scalar_fields(9)dm_test_build_pm_display_cfg_per_display(9)dm_test_build_wm_clock_ranges_dmif(9)dm_test_build_wm_clock_ranges_mcif(9)
cap clock levels:
dm_test_cap_clock_levels_engine_caps(9)dm_test_cap_clock_levels_engine_first_exceeds(9)dm_test_cap_clock_levels_memory_caps(9)dm_test_cap_clock_levels_within_limit(9)dm_test_cap_clock_levels_other_type(9)
nv clock ids:
dm_test_nv_clock_id_dispclk(9)dm_test_nv_clock_id_phyclk(9)dm_test_nv_clock_id_pixelclk(9)dm_test_nv_clock_id_invalid(9)
requirements, levels by type, latency/voltage getters:
dm_test_apply_display_requirements_dpm_enabled(9)dm_test_get_clock_levels_by_type_dpm_error(9)dm_test_get_clock_levels_by_type_success(9)dm_test_get_clock_levels_by_type_validation_fallback(9)dm_test_get_clock_levels_with_latency_success(9)dm_test_get_clock_levels_with_latency_failure(9)dm_test_get_clock_levels_with_voltage_success(9)dm_test_get_clock_levels_with_voltage_failure(9)
wm clock changes + apply clock for voltage:
dm_test_notify_wm_clock_changes_polaris(9)dm_test_notify_wm_clock_changes_non_polaris(9)dm_test_apply_clock_for_voltage_success(9)dm_test_apply_clock_for_voltage_eopnotsupp(9)dm_test_apply_clock_for_voltage_fail(9)
nv set display count / voltage by freq / pstate handshake:
dm_test_nv_set_display_count_ok(9)dm_test_nv_set_display_count_unsupported(9)dm_test_nv_set_display_count_fail(9)dm_test_nv_set_voltage_by_freq_ok(9)dm_test_nv_set_voltage_by_freq_invalid_id(9)dm_test_nv_pstate_handshake_ok(9)dm_test_nv_pstate_handshake_fail(9)
rn get dpm clock table:
dm_test_rn_get_dpm_clock_table_ok(9)dm_test_rn_get_dpm_clock_table_unsupported(9)dm_test_rn_get_dpm_clock_table_fail(9)
rv setters:
dm_test_rv_set_wm_ranges(9)dm_test_rv_set_pme_wa_enable(9)dm_test_rv_set_active_display_count(9)dm_test_rv_set_min_deep_sleep_dcfclk(9)dm_test_rv_set_hard_min_dcefclk_by_freq(9)dm_test_rv_set_hard_min_fclk_by_freq(9)
nv setters + getters (the big block, stay with me π):
dm_test_nv_set_wm_ranges(9)dm_test_nv_set_min_deep_sleep_dcfclk_ok(9)dm_test_nv_set_min_deep_sleep_dcfclk_unsupported(9)dm_test_nv_set_min_deep_sleep_dcfclk_fail(9)dm_test_nv_set_hard_min_dcefclk_ok(9)dm_test_nv_set_hard_min_dcefclk_unsupported(9)dm_test_nv_set_hard_min_dcefclk_fail(9)dm_test_nv_set_hard_min_uclk_ok(9)dm_test_nv_set_hard_min_uclk_unsupported(9)dm_test_nv_set_hard_min_uclk_fail(9)dm_test_nv_get_max_sustainable_clocks_ok(9)dm_test_nv_get_max_sustainable_clocks_unsupported(9)dm_test_nv_get_max_sustainable_clocks_fail(9)dm_test_nv_get_uclk_dpm_states_ok(9)dm_test_nv_get_uclk_dpm_states_unsupported(9)dm_test_nv_get_uclk_dpm_states_fail(9)dm_test_smu_write_watermarks_table_default(9)
see. we made it. 87 references and not a single one dropped π
and that's the page!! πβ¨ super proud of you for making it to the bottom of that SEE ALSO list, genuinely. anyway this whole thing ships from ./drivers/gpu/drm/amd/display/... and it's dated October 2026 β so yeah, mark your calendar, bestie, that's the version stamp for dm_test_get_funcs_nv(9). iykyk π¦π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms