📦 linux-manual

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I (continued)

intel_dpll_get_freq(9)calculate the DPLL's output frequency✨
intel_dpll_get_hw_state(9)readout the DPLL's hardware state✨
intel_dpll_init(9)Initialize DPLLs✨
intel_dpll_release(9)end use of DPLLs by CRTC in atomic state✨
intel_dpll_reserve(9)reserve DPLLs for CRTC and encoder combination✨
intel_dpll_swap_state(9)make atomic DPLL configuration effective✨
intel_dpll_update_active(9)update the active DPLL for a CRTC/encoder✨
intel_dpt_resume(9)restore the memory mapping for all DPT FBs during system resume✨
intel_dpt_suspend(9)suspend the memory mapping for all DPT FBs during system suspend✨
intel_drrs_activate(9)activate DRRS✨
intel_drrs_crtc_init(9)Init DRRS for CRTC✨
intel_drrs_deactivate(9)deactivate DRRS✨
intel_drrs_flush(9)Restart Idleness DRRS✨
intel_drrs_invalidate(9)Disable Idleness DRRS✨
intel_dsb_cleanup(9)To cleanup DSB context.✨
intel_dsb_commit(9)Trigger workload execution of DSB.✨
intel_dsb_prepare(9)Allocate, pin and map the DSB command buffer.✨
intel_dsb_reg_write_indexed(9)Emit indexed register write to the DSB context✨
intel_engine_cleanup_cmd_parser(9)clean up cmd parser related fields✨
intel_engine_cleanup_common(9)cleans up the engine state created by the common initializers.✨
intel_engine_cmd_parser(9)parse a batch buffer for privilege violations✨
intel_engine_context_size(9)return the size of the context for an engine✨
intel_engine_get_busy_time(9)Return current accumulated engine busyness✨
intel_engine_init_cmd_parser(9)set cmd parser related fields for an engine✨
intel_engine_is_idle(9)Report if the engine has finished process all work✨
intel_engine_reset(9)reset GPU engine to recover from a hang✨
intel_engine_reset_pinned_contexts(9)Reset the pinned contexts of an engine.✨
intel_engine_resume(9)re-initializes the HW state of the engine✨
intel_engines_init_mmio(9)allocate and prepare the Engine Command Streamers✨
intel_engines_release(9)free the resources allocated for Command Streamers✨
intel_eth_pci_probe(9)✨
intel_eth_pci_remove(9)✨
intel_fb_get_format_info(9)Get a modifier specific format information✨
intel_fb_is_ccs_aux_plane(9)Check if a framebuffer color plane is a CCS AUX plane✨
intel_fb_is_ccs_modifier(9)Check if a modifier is a CCS modifier type✨
intel_fb_is_gen12_ccs_aux_plane(9)Check if a framebuffer color plane is a GEN12 CCS AUX plane✨
intel_fb_is_mc_ccs_modifier(9)Check if a modifier is an MC CCS modifier type✨
intel_fb_is_rc_ccs_cc_modifier(9)Check if a modifier is an RC CCS CC modifier type✨
intel_fb_is_tile4_modifier(9)Check if a modifier is a tile4 modifier type✨
intel_fb_is_tiled_modifier(9)Check if a modifier is a tiled modifier type✨
intel_fb_needs_64k_phys(9)Check if modifier requires 64k physical placement.✨
intel_fb_plane_get_modifiers(9)Get the modifiers for the given platform and plane capabilities✨
intel_fb_plane_supports_modifier(9)Determine if a modifier is supported by the given plane✨
intel_fb_rc_ccs_cc_plane(9)Get the CCS CC color plane index for a framebuffer✨
intel_fbc_disable(9)disable FBC if it's associated with crtc✨
intel_fbc_handle_fifo_underrun_irq(9)disable FBC when we get a FIFO underrun✨
intel_fbc_init(9)Initialize FBC✨
intel_fbc_read_underrun_dbg_info(9)Read and log FBC-related FIFO underrun debug info✨
intel_fbc_sanitize(9)Sanitize FBC✨
intel_fdi_add_affected_crtcs(9)add CRTCs on FDI affected by other modeset CRTCs✨
intel_fdi_atomic_check_link(9)check all modeset FDI link configuration✨
intel_format_info_is_yuv_semiplanar(9)Check if the given format is YUV semiplanar✨
intel_frontbuffer_flip(9)synchronous frontbuffer flip✨
intel_frontbuffer_flush(9)flush frontbuffer object✨
intel_frontbuffer_invalidate(9)invalidate frontbuffer object✨
intel_frontbuffer_queue_flush(9)queue flushing frontbuffer object✨
intel_frontbuffer_track(9)update frontbuffer tracking✨
intel_get_dpll_by_id(9)get a DPLL given its id✨
intel_ggtt_restore_fences(9)restore fence state✨
intel_gmbus_setup(9)instantiate all Intel i2c GMBuses✨
intel_gpio_add_pin_ranges(9)add GPIO pin ranges for all groups in all communities✨
intel_gpio_to_pin(9)Translate from GPIO offset to pin number✨
intel_gt_bind_context_set_ready(9)Set the context binding as ready✨
intel_gt_bind_context_set_unready(9)Set the context binding as ready✨
intel_gt_handle_error(9)handle a gpu error✨
intel_gt_is_bind_context_ready(9)Check if context binding is ready✨
intel_gt_mcr_get_nonterminated_steering(9)find group/instance values that will steer a register to a non-terminated instance✨
intel_gt_mcr_get_ss_steering(9)returns the group/instance steering for a SS✨
intel_gt_mcr_lock(9)Acquire MCR steering lock✨
intel_gt_mcr_lock_sanitize(9)Sanitize MCR steering lock✨
intel_gt_mcr_multicast_rmw(9)Performs a multicast RMW operations✨
intel_gt_mcr_multicast_write(9)write a value to all instances of an MCR register✨
intel_gt_mcr_multicast_write_fw(9)write a value to all instances of an MCR register✨
intel_gt_mcr_read(9)read a specific instance of an MCR register✨
intel_gt_mcr_read_any(9)reads one instance of an MCR register✨
intel_gt_mcr_read_any_fw(9)reads one instance of an MCR register✨
intel_gt_mcr_unicast_write(9)write a specific instance of an MCR register✨
intel_gt_mcr_unlock(9)Release MCR steering lock✨
intel_gt_mcr_wait_for_reg(9)wait until MCR register matches expected state✨
intel_gt_reset(9)reset chip after a hang✨
intel_gt_reset_all_engines(9)Reset all engines in the given gt.✨
intel_gt_reset_engine(9)Reset a specific engine within a gt.✨
intel_guc_ads_create(9)allocates and initializes GuC ADS.✨
intel_guc_ads_reset(9)prepares GuC Additional Data Struct for reuse✨
intel_guc_allocate_and_map_vma(9)Allocate and map VMA for GuC usage✨
intel_guc_allocate_vma(9)Allocate a GGTT VMA for GuC usage✨
intel_guc_auth_huc(9)Send action to GuC to authenticate HuC ucode✨
intel_guc_ct_disable(9)Disable buffer based command transport.✨
intel_guc_ct_enable(9)Enable buffer based command transport.✨
intel_guc_ct_fini(9)Fini buffer-based communication✨
intel_guc_ct_init(9)Init buffer-based communication✨
intel_guc_ct_init_early(9)Initialize CT state without requiring device access✨
intel_guc_fw_upload(9)load GuC uCode to device✨
intel_guc_ggtt_offset(9)Get and validate the GGTT offset of @vma✨
intel_guc_load_status(9)dump information about GuC load status✨
intel_guc_log_dump(9)dump the contents of the GuC log✨
intel_guc_log_info(9)dump information about GuC log relay✨
intel_guc_resume(9)notify GuC resuming from suspend state✨
intel_guc_slpc_get_max_freq(9)Get max frequency limit for SLPC.✨
intel_guc_slpc_get_min_freq(9)Get min frequency limit for SLPC.✨
intel_guc_slpc_set_max_freq(9)Set max frequency limit for SLPC.✨
intel_guc_slpc_set_min_freq(9)Set min frequency limit for SLPC.✨
intel_guc_suspend(9)notify GuC entering suspend state✨
intel_gvt_activate_vgpu(9)activate a virtual GPU✨
intel_gvt_clean_device(9)clean a GVT device✨
intel_gvt_clean_gtt(9)clean up mm components of a GVT device✨
intel_gvt_clean_mmio_info(9)clean up MMIO information table for GVT device✨
intel_gvt_create_idle_vgpu(9)create an idle virtual GPU✨
intel_gvt_deactivate_vgpu(9)deactivate a virtual GPU✨
intel_gvt_debugfs_add_vgpu(9)register debugfs entries for a vGPU✨
intel_gvt_debugfs_clean(9)remove debugfs entries✨
intel_gvt_debugfs_init(9)register gvt debugfs root entry✨
intel_gvt_debugfs_remove_vgpu(9)remove debugfs entries of a vGPU✨
intel_gvt_destroy_idle_vgpu(9)destroy an idle virtual GPU✨
intel_gvt_destroy_vgpu(9)destroy a virtual GPU✨
intel_gvt_driver_remove(9)cleanup GVT components when i915 driver is unbinding✨
intel_gvt_for_each_tracked_mmio(9)iterate each tracked mmio✨
intel_gvt_free_firmware(9)free GVT firmware✨
intel_gvt_i2c_handle_aux_ch_write(9)emulate AUX channel register write✨
intel_gvt_i2c_handle_gmbus_read(9)emulate gmbus register mmio read✨
intel_gvt_i2c_handle_gmbus_write(9)emulate gmbus register mmio write✨
intel_gvt_init(9)initialize GVT components✨
intel_gvt_init_device(9)initialize a GVT device✨
intel_gvt_init_engine_mmio_context(9)Initiate the engine mmio list✨
intel_gvt_init_gtt(9)initialize mm components of a GVT device✨
intel_gvt_init_irq(9)initialize GVT-g IRQ emulation subsystem✨
intel_gvt_init_vgpu_types(9)initialize vGPU type list✨
intel_gvt_iterate_mmio_table(9)Iterate the GVT MMIO table✨
intel_gvt_load_firmware(9)load GVT firmware✨
intel_gvt_mmio_has_mode_mask(9)if a MMIO has a mode mask✨
intel_gvt_mmio_is_cmd_accessible(9)if a MMIO could be accessed by command✨
intel_gvt_mmio_is_cmd_write_patch(9)check if an mmio's cmd access needs to be patched✨
intel_gvt_mmio_is_sr_in_ctx(9)check if an MMIO has F_SR_IN_CTX mask✨
intel_gvt_mmio_is_unalign(9)mark a MMIO could be accessed unaligned✨
intel_gvt_mmio_set_accessed(9)mark a MMIO has been accessed✨
intel_gvt_mmio_set_cmd_accessible(9)mark a MMIO could be accessible by command✨
intel_gvt_mmio_set_cmd_write_patch(9)mark an MMIO if its cmd write needs to be patched✨
intel_gvt_mmio_set_sr_in_ctx(9)mask an MMIO in GVT's mmio save-restore list and also in hardware logical context image✨
intel_gvt_read_gpa(9)copy data from GPA to host data buffer✨
intel_gvt_release_vgpu(9)release a virtual GPU✨
intel_gvt_render_mmio_to_engine(9)convert a mmio offset into the engine✨
intel_gvt_reset_vgpu(9)reset a virtual GPU (Function Level)✨
intel_gvt_reset_vgpu_locked(9)reset a virtual GPU by DMLR or GT reset✨
intel_gvt_restore_ggtt(9)restore all vGPU's ggtt entries✨
intel_gvt_resume(9)GVT resume routine wrapper✨
intel_gvt_scan_and_shadow_workload(9)audit the workload by scanning and shadow it as well, include ringbuffer,wa_ctx and ctx.✨
intel_gvt_setup_mmio_info(9)setup MMIO information table for GVT device✨
intel_gvt_switch_mmio(9)switch mmio context of specific engine✨
intel_gvt_write_gpa(9)copy data from host data buffer to GPA✨
intel_hfi_offline(9)Disable HFI on @cpu✨
intel_hfi_online(9)Enable HFI on @cpu✨
intel_hpd_block(9)Block handling of HPD IRQs on an HPD pin✨
intel_hpd_clear_and_unblock(9)Unblock handling of new HPD IRQs on an HPD pin✨
intel_hpd_init(9)initializes and enables hpd support✨
intel_hpd_irq_handler(9)main hotplug irq handler✨
intel_hpd_irq_storm_detect(9)gather stats and detect HPD IRQ storm on a pin✨
intel_hpd_pin_default(9)return default pin associated with certain port.✨
intel_hpd_poll_disable(9)disable polling for connectors with hpd✨
intel_hpd_poll_enable(9)enable polling for connectors with hpd✨
intel_hpd_trigger_irq(9)trigger an hpd irq event for a port✨
intel_hpd_unblock(9)Unblock handling of HPD IRQs on an HPD pin✨
intel_huc_auth(9)Authenticate HuC uCode✨
intel_huc_check_status(9)check HuC status✨
intel_huc_fw_upload(9)load HuC uCode to device via DMA transfer✨
intel_huc_load_status(9)dump information about HuC load status✨
intel_idle(9)Ask the processor to enter the given idle state.✨
intel_idle_cpu_init(9)Register the target CPU with the cpuidle core.✨
intel_idle_cpuidle_devices_uninit(9)Unregister all cpuidle devices.✨
intel_idle_cpuidle_driver_init(9)Create the list of available idle states.✨
intel_idle_cst_usable(9)Check if the _CST information can be used.✨
intel_idle_s2idle(9)Ask the processor to enter the given idle state.✨
intel_init_cdclk_hooks(9)Initialize CDCLK related modesetting hooks✨
intel_init_display_hooks(9)initialize the display modesetting hooks✨
intel_iommu_drain_pasid_prq(9)Drain page requests and responses for a pasid✨
intel_irq_fini(9)deinitializes IRQ support✨
intel_irq_init(9)initializes irq support✨
intel_irq_install(9)enables the hardware interrupt✨
intel_irq_resume(9)Resume interrupts✨
intel_irq_suspend(9)Suspend interrupts✨
intel_irq_uninstall(9)finalizes all irq handling✨
INTEL_LB_FLAG_IS_PERSISTENT(9)Mark the payload as persistent✨
intel_link_bw_atomic_check(9)check display link states and set a fallback config if needed✨
intel_link_bw_compute_pipe_bpp(9)compute pipe bpp limited by max link bpp✨
intel_link_bw_init_limits(9)initialize BW limits✨
intel_link_bw_set_bpp_limit_for_pipe(9)set link bpp limit for a pipe to its minimum✨
intel_lpe_audio_init(9)detect and setup the bridge between HDMI LPE Audio driver and i915✨
intel_lpe_audio_irq_handler(9)forwards the LPE audio irq✨
intel_lpe_audio_notify(9)notify lpe audio event audio driver and i915✨
intel_lpe_audio_teardown(9)destroy the bridge between HDMI LPE audio driver and i915✨
intel_lvds_init(9)setup LVDS connectors on this device✨
intel_match_g8_cpu(9)match current CPU against g8_cpu_ids✨
intel_memory_region_reserve(9)Reserve a memory range✨
intel_microcode_sanity_check(9)Sanity check microcode file.✨
intel_mid_pci_init(9)installs intel_mid_pci_ops✨
intel_modeset_all_pipes_late(9)force a full modeset on all pipes✨
intel_modeset_pipes_in_mask_early(9)force a full modeset on a set of pipes✨
intel_opregion_get_edid(9)Fetch EDID from ACPI OpRegion mailbox #5✨
intel_pasid_setup_nested(9)Set up PASID entry for nested translation.✨
intel_pch_fifo_underrun_irq_handler(9)handle PCH fifo underrun interrupt✨
intel_pin_to_gpio(9)Translate from pin number to GPIO offset✨