intel_gvt_mm...et_sr_in_ctx(9)

💖 NAME 💖

okay bestie, welcome to the Kernel API Manual page for intel_gvt_mmio_set_sr_in_ctx(9) — yes, the header does its lil truncation thing, but we're using the full name here, periodt. This function masks an MMIO in GVT's mmio save-restore list and also in the hardware logical context image. That's the whole vibe: mask an MMIO in both places. ✨

🦋 SYNOPSIS 🦋

void intel_gvt_mmio_set_sr_in_ctx (struct intel_gvt *gvt , unsigned int
       offset );

🎀 ARGUMENTS 🎀

• gvt — a GVT device. That's it, bestie, it's the GVT device you're working with. 🫶
• offset — register offset. The offset of the register, no cap. 📍

🌸 SEE ALSO 🌸

Go peek at the kernel file ./drivers/gpu/drm/i915/gvt/gvt.h and these iconic functions:

• intel_gvt_mmio_set_accessed(9)
• intel_gvt_mmio_is_cmd_accessible(9)
• intel_gvt_mmio_set_cmd_accessible(9)
• intel_gvt_mmio_is_unalign(9)
• intel_gvt_mmio_has_mode_mask(9)
• intel_gvt_mmio_is_sr_in_ctx(9)
• intel_gvt_mmio_set_cmd_write_patch(9)
• intel_gvt_mmio_is_cmd_write_patch(9)
• intel_gvt_read_gpa(9)
• intel_gvt_write_gpa(9)

okay that's the whole page, bestie — source/version path is ./drivers/gpu/drm/i915/gvt, dated October 2026. slay 💅✨