📦 perl-verilog-perl

V

• Verilog::EditFiles(3pm)Split Verilog modules into separate files.✨
• Verilog::Getopt(3pm)Get Verilog command line options✨
• Verilog::Language(3pm)Verilog language utilities✨
• Verilog::Netlist(3pm)Verilog Netlist✨
• Verilog::Netlist::Cell(3pm)Instantiated cell within a Verilog Netlist✨
• Verilog::Netlist::ContAssign(3pm)ContAssign assignment✨
• Verilog::Netlist::Defparam(3pm)Defparam assignment✨
• Verilog::Netlist::File(3pm)File containing Verilog code✨
• Verilog::Netlist::Interface(3pm)Interface within a Verilog Netlist✨
• Verilog::Netlist::Logger(3pm)Error collection and reporting✨
• Verilog::Netlist::ModPort(3pm)ModPort within a Verilog Interface✨
• Verilog::Netlist::Module(3pm)Module within a Verilog Netlist✨
• Verilog::Netlist::Net(3pm)Net for a Verilog Module✨
• Verilog::Netlist::Pin(3pm)Pin on a Verilog Cell✨
• Verilog::Netlist::PinSelection(3pm)Nets attached to a Verilog Cell's Pins✨
• Verilog::Netlist::Port(3pm)Port for a Verilog Module✨
• Verilog::Netlist::Subclass(3pm)Common routines for all classes✨
• Verilog::Parser(3pm)Parse Verilog language files✨
• Verilog::Preproc(3pm)Preprocess Verilog files✨
• Verilog::SigParser(3pm)Signal Parsing for Verilog language files✨
• Verilog::Std(3pm)SystemVerilog Built-in std Package Definition✨
• vhier(1)Return all files in a verilog hierarchy using Verilog::Netlist✨
• vpassert(1)Preprocess Verilog code assertions✨
• vppreproc(1)Preprocess Verilog code using verilog-perl✨
• vrename(1)change signal names across many Verilog files✨