Std(3)

💖 Std(3) — Verilog::Std 💖

okay bestie, welcome to the User Contributed Perl Documentation page for Std(3), aka Verilog::Std — the SystemVerilog Built-in std Package Definition. no cap, this is the whole vibe 💅

---

✨ NAME ✨

Verilog::Std — SystemVerilog Built-in std Package Definition 🦋

🌸 SYNOPSIS 🌸

Internally used by Verilog::SigParser, etc. 👀

use Verilog::Std;
print Verilog::Std::std;

💅 DESCRIPTION 💅

Verilog::Std contains the built-in std package required by the SystemVerilog standard. that's it, that's the tea 🍓

🎀 FUNCTIONS 🎀

• std({standard}) — returns the definition of the std package. optionally pass the language standard; if you don't, it defaults to whatever Verilog::Language::language_standard returns. periodt ✨

🦋 DISTRIBUTION 🦋

Verilog-Perl is part of the https://www.veripool.org/ free Verilog EDA software tool suite. the latest version is available from CPAN and from https://www.veripool.org/verilog-perl 🌈

Copyright 2009-2024 by Wilson Snyder. this package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0 📜

👑 AUTHORS 👑

Wilson Snyder <wsnyder@wsnyder.org> 👑

🌈 SEE ALSO 🌈

Verilog-Perl 🫶

---

kisses bestie, this page was brought to you by perl v5.42.0 on 2025-07-25, and yes, it's still the Std(3) page 💖💅